Reservoir Computing Device Using {-1, 0, 1} Matrix Shift Operations
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Solution Overview
Problem
Reservoir computing models with recurrent network architectures face complex calculations, leading to high power consumption, large hardware requirements, and increased costs, which hinder miniaturization and deployment in resource-constrained environments.
Innovation Solution
A computing device that simplifies calculations by using an interconnectivity-representation matrix with elements set to 1, 0, or −1, performing shift operations, and applying a polynomial activation function, reducing the need for multipliers and enabling calculations with adders and shift registers, thereby decreasing power consumption and hardware size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional reservoir computing models with recurrent network architectures are used, then information processing capability is achieved, but calculation complexity increases leading to high power consumption and large hardware requirements
Solution Approach 1:
The patent changes the parameter values in the interconnectivity-representation matrix to be restricted to {-1, 0, 1}, which fundamentally alters the calculation operations from general multiplication to simpler addition/subtraction operations. This parameter restriction enables the use of adders instead of multipliers, directly reducing power consumption and hardware complexity while maintaining the recurrent network's information processing capability
Solution Approach 2:
The patent substitutes complex multiplication operations with addition and shift operations. By representing matrix elements as {-1, 0, 1} and using shift operations on binary representations, the system replaces power-intensive multiplier circuits with simpler adder circuits and shift registers, achieving the same computational function with reduced hardware complexity and power consumption
2Area of stationary object
If conventional reservoir computing models are deployed, then computing functionality is provided, but hardware size and costs increase
Solution Approach 1:
By constraining matrix parameters to {-1, 0, 1}, the patent eliminates the need for complex multiplier circuits that occupy significant hardware area. The simplified operations can be implemented using compact adder circuits and shift registers, directly reducing the hardware footprint while maintaining computational functionality
Solution Approach 2:
The patent extracts and eliminates the multiplication operation from the computational model, retaining only addition and shift operations. This extraction of the complex multiplication step removes the need for large multiplier circuits, significantly reducing hardware size and deployment costs
Data Source
AI summary
A computing device calculates a product between an interconnectivity-representation matrix including a plurality of elements having values each set to 1, 0, or −1 and a vector representing values of intermediate nodes, carries out a shift operation with a bit string in binary notation for each element among a plurality of elements of a vector obtained by the product, makes summation of a vector obtained by the shift operation and a vector including weighted input values, applies a function, which is determined as an activation function, for each element among a plurality of elements of a vector obtained by the summation of the vector obtained by the shift operation and the vector having the weighted input values, thus calculating a vector representing the values of the intermediate nodes updated in timestep progression, and calculates a plurality of output values by weighting the updated values of the intermediate nodes.