Reset Signal Path Prediction for Multicycle Circuit Emulation
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Solution Overview
Problem
Existing circuit emulation systems face performance bottlenecks and glitches due to direct evaluation of reset signals without prediction, leading to unintended design state changes and reduced emulation performance.
Innovation Solution
Implement multicycle path prediction for reset signals by remodeling secondary clock signals based on a primary clock signal, applying prediction to reset logic cones to mitigate glitches and improve emulation performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reset signals are directly evaluated without prediction in circuit emulation, then the emulation follows the actual circuit behavior, but performance bottlenecks and glitches occur reducing emulation efficiency
Solution Approach 1:
The patent applies prediction to reset signals by evaluating them one or more clock cycles in advance of their actual arrival time. This preliminary action allows the emulation system to prepare for upcoming reset events, avoiding performance bottlenecks and glitches that would occur with direct evaluation, thereby maintaining both accuracy and high emulation performance
2Productivity
If reset signals are predicted one or more clock cycles in advance, then emulation performance improves, but the complexity of the emulation system increases
Solution Approach 1:
The patent introduces a prediction mechanism as an intermediary between the actual reset signal generation and the emulation evaluation. This intermediary component evaluates reset signals in advance and provides predicted values to the emulation system, improving performance while containing complexity through a structured intermediate layer rather than fundamentally redesigning the entire emulation architecture
3Stability of the object's composition
If multicycle path prediction is applied to reset signals, then glitches are mitigated and state changes are stabilized, but the processing overhead increases
Solution Approach 1:
By evaluating reset signals one or more clock cycles in advance, the system performs the prediction work preliminarily, allowing stable state changes to propagate through the circuit without glitches. The advance evaluation distributes the processing load over multiple cycles rather than concentrating it at the moment of reset, thereby stabilizing states while managing processing overhead
Data Source
AI summary
A system and method for emulation receives a circuit design driven by a primary clock signal. The circuit design includes reset circuitry and sequential circuitry connected to the reset circuitry. The circuit design includes a secondary clock signal that is slower than the primary clock signal. The reset circuitry generates a reset signal that is a function of the secondary clock signal. The secondary clock signal is remodeled at a transition edge of the primary clock signal, and a predicted reset signal is generated subsequent to the reset signal at the transition edge of the primary clock signal. An operation of the circuit design is emulated based on the predicted reset signal such that the predicted reset signal from the reset circuitry propagates through multiple cycles of the primary clock signal.