Resistance Change Memory Flag Control for Erase Durability
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Solution Overview
Problem
Resistance change memory devices face durability issues due to unnecessary rewriting actions when attempting to emulate flash memory's erasure and programming commands, as they reset all memory cells to '1' regardless of their initial state, leading to inefficient use of rewriting limits.
Innovation Solution
A semiconductor memory device with a flag system that differentiates between erasure and non-erasure states, allowing for selective output of data based on flag data during reading and programming, reducing unnecessary rewriting by maintaining the original data in memory cells storing '1' during block erasure and programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If block erasure is performed by resetting all memory cells to '1' state, then flash memory compatibility is achieved, but unnecessary rewriting actions occur consuming rewriting limit and deteriorating durability
Solution Approach 1:
The patent segments the memory block into individual memory cells and introduces a flag register for each cell to track its initial state. This allows selective erasure of only those cells that were in the '0' state, avoiding unnecessary rewriting of cells already in the '1' state, thus resolving the contradiction between flash compatibility and durability.
Solution Approach 2:
The patent performs a preliminary read operation before erasure to detect the initial state of each memory cell. Based on this preliminary information stored in flag registers, the system determines which cells require erasure, preventing unnecessary rewriting actions and preserving memory cell durability while maintaining flash compatibility.
2Ease of operation
If all memory cells are reset during block erasure regardless of initial state, then erasure command functionality is provided, but rewriting limit is consumed inefficiently
Solution Approach 1:
The patent implements a feedback mechanism where the initial state of each memory cell is read and stored in a flag register before erasure. This feedback information guides the erasure operation, enabling the system to selectively erase only the necessary cells and avoid consuming rewriting limit on cells that don't require erasure, thus improving rewriting efficiency while maintaining full erasure functionality.
Data Source
AI summary
A semiconductor memory device for suppressing a decrease of durability caused by erasure of a block unit or programming of a word unit is provided. A resistance change memory 100 includes a memory array 110 and a controller 120. The memory array 110 stores data by a reversible and nonvolatile variable resistance element. When erasing a selected block of the memory array 110 in response to an external erasure command, the controller 120 sets an EF flag indicating the selected block is in an erasure state without changing block data. The controller 120 further includes a reading unit. The reading unit outputs data of a selected word or data indicating the erasure based on the EF flag when reading the selected word of the memory array 110 in response to an external reading command.