Variable Resistance Memory Cell Side Surface Insulator
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Solution Overview
Problem
Conventional resistive RAM (ReRAM) memory devices face challenges in achieving high integration and reducing power consumption due to the large current required for resistance state changes and voltage drops across interconnects, which complicates the miniaturization of memory cells and increases power consumption.
Innovation Solution
The memory device employs a multilayer structure with a variable resistance material formed on the side surfaces of an insulator, rather than surrounding the entire multilayer structure, allowing for a smaller sectional area and reduced current requirements, and uses atomic layer deposition for uniform film thickness, thereby decreasing power consumption and voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the variable resistance material surrounds the entire multilayer structure, then the resistance state change is achieved, but the current required is large and power consumption increases
Solution Approach 1:
The variable resistance material is selectively positioned only on the side surfaces of the insulator rather than surrounding the entire multilayer structure. This localized placement concentrates the resistance change function in specific regions, reducing the total volume of variable resistance material needed and thereby decreasing the current and power consumption required for resistance state changes.
Solution Approach 2:
The variable resistance material is divided into discrete segments positioned on specific side surfaces of the insulator rather than forming a continuous surrounding layer. This segmentation allows for optimized current paths and reduces the total amount of material involved in the resistance change process, leading to lower power consumption.
2Reliability
If the variable resistance material surrounds the entire multilayer structure, then the resistance state change is achieved, but the sectional area becomes large which complicates miniaturization
Solution Approach 1:
The variable resistance material is selectively positioned only on the side surfaces of the insulator rather than surrounding the entire multilayer structure. This localized placement concentrates the resistance change function in specific regions, reducing the total volume of variable resistance material needed and thereby decreasing the current and power consumption required for resistance state changes.
Solution Approach 2:
The variable resistance material is positioned on vertical side surfaces of the insulator rather than forming a horizontal surrounding layer. This dimensional transition from a planar configuration to a vertical configuration reduces the footprint area while maintaining the functional volume, enabling miniaturization of the memory cell.
3Reliability
If conventional ReRAM structure is used, then memory cell is formed, but voltage drops across interconnects increases power consumption
Solution Approach 1:
The variable resistance material is divided into discrete segments positioned on specific side surfaces of the insulator rather than forming a continuous surrounding layer. This segmentation allows for optimized current paths and reduces the total amount of material involved in the resistance change process, leading to lower power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a significant reduction in the current needed for resistance changes and power consumption, while maintaining high integration density, and prevents dielectric breakdown, allowing for efficient and low-power memory storage.
Implementation Method 1
uses atomic layer deposition for uniform film thickness
Data Source
AI summary
According to one embodiment, a memory device includes first interconnects, second interconnects, and a first memory cell. The first memory cell is located in an intersection of one of the first interconnects and one of the second interconnects. The first memory cell includes a first multilayer structure and a first variable resistance layer, the first multilayer structure including a first electrode, a first selector, and a first insulator which are stacked. The first selector and the first variable resistance layer are electrically connected in series between the one of the first interconnect and the one of the second interconnect. The first variable resistance layer is formed on a portion of a side surface of the first insulator to cover the portion without covering a residual portion.


