Resistance Memory Device with Tungsten Oxide for Multi-Bit Storage
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Solution Overview
Problem
Current memory devices struggle to efficiently support multiple-bit storage and thermal stability for high-capacity, quick data transmission in portable digital devices, particularly in varying environmental conditions.
Innovation Solution
A resistance type memory device utilizing a tungsten oxide layer between conductors, with adjustable resistivity through pulse voltage application, enabling multiple-bit storage and integration into both volatile and non-volatile memory systems, and employing self-aligned manufacturing for ease of integration into existing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory devices are used, then single-bit storage is achieved, but storage capacity is limited
Solution Approach 1:
The patent applies parameter changes by utilizing multiple resistivity states (first, second, and third resistivity) of the metal oxide layer to represent multiple bits of data. By controlling the resistance value through pulse voltage application, the device can store 2 bits or more in a single memory cell, thereby increasing storage capacity without proportionally increasing device complexity
Solution Approach 2:
The memory device achieves multi-functionality by enabling both volatile and non-volatile memory operations through the same metal oxide layer structure. The device can operate in different storage modes (first storage state, second storage state, third storage state) depending on the pulse voltage application, providing versatile storage solutions
2Quantity of substance
If high-capacity storage is implemented, then data transmission capacity increases, but thermal stability deteriorates
Solution Approach 1:
The patent employs a metal oxide layer that can be repeatedly programmed and erased through pulse voltage application. The metal oxide material allows for multiple writing operations to achieve high-capacity storage while maintaining thermal stability through its inherent material properties and controlled resistivity states
3Productivity
If multiple-bit storage is achieved, then storage efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple functions into a single memory cell structure consisting of conductors and a metal oxide layer. By combining the storage of multiple bits and the control mechanisms within one cell, the device achieves high storage efficiency while maintaining relatively simple manufacturing processes that can be integrated into existing fabrication lines
4Speed
If rapid programming operations are implemented, then data transmission speed increases, but energy consumption increases
Solution Approach 1:
The patent utilizes periodic pulse voltage application to program the metal oxide layer into different resistivity states. By applying controlled pulses with specific timing and duration, the device achieves rapid programming operations while optimizing energy consumption through the periodic nature of the voltage application rather than continuous power supply
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves multiple-bit storage with high thermal stability, allowing for efficient data storage across various temperatures and enabling rapid programming operations, thus addressing the limitations of existing memory technologies.
Implementation Method 1
The resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer.
Data Source
AI summary
A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity.