Resistive Memory Clamping Unit for Precharge Offset Cancellation

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Solution Overview

Problem

Current memory devices face challenges in securing a sensing margin while reducing power consumption, particularly due to precharge offsets generated during the reading process in resistive memory cells.

Innovation Solution

A memory device design that includes a clamping unit with a transistor and capacitor, which ramps up the voltage of a first node in a first precharge mode and adjusts the voltage level of a second node in a second precharge mode using switches to cancel precharge offsets, thereby enhancing sensing margin and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a conventional reading operation is performed in resistive memory cells, then data can be read from the memory cell, but precharge offsets are generated that reduce sensing margin and increase power consumption

Engineering Contradiction:
Improvesensing marginVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by performing a precharge operation before the actual read operation. The sensing node is precharged to a predetermined voltage level (e.g., VDD/2) before the read cycle begins. This preliminary charging action establishes a known initial state that eliminates uncertain precharge offsets during the actual reading process, thereby improving sensing margin while controlling power consumption through regulated precharge timing and voltage levels.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms through sense amplifiers that detect the voltage level at the sensing node and generate corresponding output signals. The sense amplifier monitors the voltage difference between the sensing node and reference voltage, providing feedback information about the memory cell state. This feedback enables accurate data detection while the control circuit regulates power supply based on operational status, optimizing the balance between sensing precision and power consumption.

Inventive Principle:
Principle #23Feedback

2Reliability

If precharge offsets are not canceled, then the reading process can proceed, but the sensing margin is reduced affecting data accuracy

Engineering Contradiction:
Improvedata accuracyVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses preliminary action by precharging the sensing node to a predetermined voltage level before the read operation. This precharge step establishes a known initial state that eliminates uncertain precharge offsets during the actual reading process. The control circuit manages the precharge timing and voltage levels to ensure accurate data reading without requiring complex offset cancellation circuits, thereby improving data accuracy while maintaining reasonable circuit complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary approach by using a dedicated sense amplifier circuit as a mediator between the memory cell and the output. The sense amplifier acts as an intermediary that processes the voltage signal from the sensing node, comparing it against reference voltages and generating standardized output signals. This intermediary processing layer simplifies the overall circuit design by centralizing the signal processing function, making it easier to manage and optimize for both reliability and complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10102897B2Memory device and method of operating the same
Publication Date: 2018.10.16 SAMSUNG ELECTRONICS CO LTD
  • US10102897B2 patent drawing
  • US10102897B2 patent drawing
  • US10102897B2 patent drawing

AI summary

A memory device includes: a resistive memory cell connected to a first node; a current supply unit providing to a sensing node a comparison current to be compared with a cell current flowing through the first node to read data stored in the resistive memory cell; a clamping unit connected between the sensing node and the first node and including a transistor and a capacitor connected to a gate of the transistor via a second node; and a sense amplifier sensing the sensing node voltage and transitioning an output value when the sensing node voltage is less than a reference voltage. The clamping unit receives a first read voltage and a boost voltage, ramps up a voltage of the first node in a first precharge mode, and adjusts a level of a second read voltage of the second node in a second precharge mode.