Resistive Memory Common Source with Low Resistance Conductor
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Solution Overview
Problem
Resistive memory device arrays face challenges in achieving low common source resistance and high drivability, which are essential for maintaining operating speed and performance, especially when dealing with high current requirements during programming and erasing processes.
Innovation Solution
The implementation of a semiconductor device with a substrate and multiple source regions connected by elongated conductors that form a common source, reducing common source resistance while enabling high current drivability through minimal substrate area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common source configuration is used in resistive memory device arrays, then device complexity is reduced and manufacturing is simplified, but common source resistance increases causing voltage drop and reduced operating speed
Solution Approach 1:
The common source region is segmented into multiple discrete source regions (first source region, second source region, etc.) that are spatially distributed across the substrate. Each source region is independently connected to the common source line, dividing the current path and reducing the effective resistance experienced by any single memory cell while maintaining the overall common source architecture.
Solution Approach 2:
The patent transitions from a planar common source configuration to a three-dimensional arrangement by positioning source regions at different locations on the substrate and connecting them via vertical contacts to a common source line. This spatial distribution in multiple dimensions reduces current crowding and resistance while preserving the common source topology.
2Area of stationary object
If traditional common source connections are used, then substrate area is minimized, but current carrying capacity is insufficient for high-current resistive memory operations
Solution Approach 1:
Multiple source regions are merged into a unified common source system where individual source regions are distributed across the substrate but electrically connected to a shared common source line. This combining approach allows each source region to handle local current demands while the common source line aggregates the total current capacity, achieving high current handling without proportionally increasing substrate area.
Solution Approach 2:
The patent implements local source regions with optimized dimensions and positions tailored to local current density requirements. Each source region can be independently sized and shaped to match the specific current demands of adjacent memory cells, while the common source line provides centralized current collection. This local optimization enables high current capacity within minimal substrate footprint.
Data Source
AI summary
In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. In one embodiment, the conductor is an elongated metal body of T-shaped cross-section. In another embodiment, the conductor is a plate-like metal body.