Resistive Memory Circuit with Complementary States
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Solution Overview
Problem
Controlling current spikes during state changes in resistive memory elements is challenging, posing risks to the operation of resistive memory elements and other elements in circuit structures.
Innovation Solution
A circuit structure incorporating two resistive memory elements in opposite memory states, with a drive transistor and a read transistor, allowing for controlled write and read operations by enabling current flow through one element while disabling it through the other, thereby preventing accidental data changes and reducing current spikes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current flow is enabled through resistive memory element during write operation, then data can be programmed, but current spike may damage the resistive memory element and other circuit elements
Solution Approach 1:
The patent introduces a current limiting circuit as an intermediary component between the write voltage source and the resistive memory element. This circuit actively monitors and limits the current flow during write operations, preventing current spikes from reaching levels that could damage the memory element or surrounding circuitry, thus resolving the contradiction between enabling write operations and preventing harmful current spikes
Solution Approach 2:
The patent implements protective circuitry that is pre-configured to cushion against potential current spikes before they can cause damage. The current limiting circuit and protective elements are designed to activate automatically during write operations, providing beforehand protection that allows aggressive write voltages to be applied without risking damage to the memory element
2Device complexity
If single resistive memory element is used, then circuit complexity is reduced, but data reliability and control accuracy deteriorate
Solution Approach 1:
The patent divides the memory cell into two separate resistive memory elements (first and second memory elements) with distinct functions. The first memory element stores the data bit while the second memory element serves as a reference or complementary element. This segmentation improves reliability by enabling differential read operations and better state control, while the overall cell structure remains relatively simple
Solution Approach 2:
The patent combines multiple functional components (drive transistor, read transistor, two resistive memory elements) into a single integrated memory cell structure. This merging approach achieves improved reliability through the complementary configuration while maintaining compactness and avoiding excessive complexity in the overall circuit architecture
3Speed
If high current is applied to switch memory state, then switching speed is improved, but harmful current spikes are generated
Solution Approach 1:
The current limiting circuit acts as an intermediary that allows high current to flow quickly for fast switching while simultaneously preventing current from exceeding safe thresholds. The circuit dynamically adjusts current levels during the switching transient, enabling fast state changes without generating damaging current spikes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures accurate data storage and retrieval by maintaining complementary memory states, reducing the risk of data alteration and current spikes, and allowing for efficient read and write operations in resistive random access memory (ReRAM) circuits.
Implementation Method 1
Depending on the direction of current flows across the dielectric material from one terminal to the other, the current may cause ions to form within the dielectric alongside one of the terminals. This formation/disruption may substantially decrease/increase the electrical resistance across the resistive memory element.
Implementation Method 2
Resistive random access memory (ReRAM) is an emerging and appealing sector of digital memory technology. ReRAM technology may use programmable elements of variable resistance to indicate high and low voltages.
Implementation Method 3
a drive transistor having a source terminal, a drain terminal, and a gate terminal coupled to a word line
Implementation Method 4
a read transistor having a source terminal coupled to the drain terminal of the drive transistor, a drain terminal coupled to ground, and a gate terminal coupled to a select line
Data Source
AI summary
The disclosure provides a circuit structure for storage and retrieval of data, and related methods. The circuit structure may include drive transistor having a source terminal, a drain terminal, and a gate terminal coupled to a word line. A first resistive memory element coupled between the source terminal of the drive transistor and a first bit line may be in a first memory state. A second resistive memory element coupled between the drain terminal of the drive transistor and a second bit line may be in a second memory state opposite the first memory state. The structure may also include a read transistor having a source terminal coupled to the drain terminal of the drive transistor, a drain terminal coupled to ground, and a gate terminal coupled to a select line.