Resistive Memory Connection Paths for Signal Delay and Peak Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Resistive memory devices with cross-point array structures face challenges in simultaneously compensating for current concentration in near memory cells and signal delay in far memory cells, particularly due to peak currents generated during phase change operations.
Innovation Solution
The implementation of a resistive memory device with a semiconductor substrate featuring MAT regions, row control regions, and column control regions, where word lines and bit lines are arranged with uniform gaps and overlapping structures, and connection paths with a direct structure instead of spiral bypass structures to manage signal transmission and reduce peak currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If spiral bypass connection paths are used to increase connection resistance, then peak current damages are reduced, but signal delay increases
Solution Approach 1:
The patent changes the geometric parameters of the connection path from a spiral bypass structure to a direct structure with optimized dimensions. The direct connection path has a width and length that provide sufficient connection resistance to limit peak current, while the direct geometry minimizes the signal transmission path length, thereby reducing signal delay compared to spiral paths.
Solution Approach 2:
Instead of using a spiral bypass path that indirectly connects word lines to control elements (which increases path length and signal delay), the patent inverts the approach by using a direct connection path that shortens the transmission path while still providing adequate resistance through optimized dimensional parameters.
2Productivity
If uniform gap arrangement of word lines is used, then layout efficiency is improved, but current concentration in near memory cells increases
Solution Approach 1:
The patent maintains uniform gap arrangement for overall layout efficiency, but applies local quality adjustments through the connection path design. The direct connection paths are positioned and dimensioned to distribute current more evenly, reducing concentration in near memory cells while preserving the uniform periodic structure beneficial for layout efficiency.
3Loss of time
If direct connection paths are used instead of spiral bypass structures, then signal delay is reduced, but connection resistance decreases
Solution Approach 1:
The patent compensates for the reduced connection resistance of direct paths by optimizing their dimensional parameters. The width and length of the direct connection paths are specifically designed to provide sufficient resistance for limiting peak current, while the direct geometry maintains short signal transmission paths for reduced delay.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the layout efficiency and reduces signal delays and peak current damages by increasing connection resistance, thereby improving the operational stability and reliability of phase changeable memory cells.
Implementation Method 1
Resistive memory devices, including phase changeable memory devices, may use a phase changeable material as a data storage medium
Implementation Method 2
The data storage medium and the switching element including the phase changeable material may be located at intersected points between word lines and bit lines
Data Source
AI summary
A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.