Resistive Memory Device With Position-Dependent Contact Resistance
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Solution Overview
Problem
Resistive memory devices with a three-dimensional cross-point stacked structure face reliability issues due to voltage drops (IR drops) as their speed and capacity increase, affecting their performance.
Innovation Solution
The resistive memory device incorporates a design with first and second heating electrode layers having different contact resistances, strategically placed in regions closer and farther from the access point, to manage voltage drops and maintain heating efficiency across the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the speed and capacity of the resistive memory device are increased, then the performance of the memory device is improved, but the reliability of the memory device is reduced due to IR drop
Solution Approach 1:
The patent applies local quality by making the contact resistance of heating electrode layers position-dependent within the memory cell array. Memory cells closer to the access point have lower contact resistance, while those farther away have higher contact resistance. This localized variation compensates for IR drop effects that increase with distance from the access point, thereby maintaining reliable operation across the entire array while supporting higher speed and capacity.
2Quantity of substance
If memory cells are placed farther from the access point to increase capacity, then the storage capacity is improved, but the voltage drop increases reducing heating efficiency
Solution Approach 1:
The patent implements local quality by varying the contact resistance of heating electrode layers based on their position relative to the access point. Memory cells located farther from the access point, which experience greater voltage drop and reduced heating efficiency, are equipped with heating electrode layers having higher contact resistance. This local adjustment compensates for the reduced voltage, maintaining adequate heating efficiency throughout the expanded memory array and enabling increased storage capacity.
Solution Approach 2:
The patent applies parameter changes by modifying the contact resistance parameter of heating electrode layers as a function of position within the memory cell array. By changing this electrical parameter locally, the system compensates for position-dependent voltage drops and maintains consistent heating efficiency across the entire array, enabling expanded capacity without sacrificing performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design compensates for voltage drops, enhancing the reliability, speed, and capacity of the memory device by ensuring consistent heating power across all regions, regardless of distance from the access point.
Implementation Method 1
a first memory cell comprising a first resistive memory layer and a first heating electrode layer, the first heating electrode layer comprises a first contact surface in contact with the first resistive memory layer and the first contact surface has a first contact resistance
Data Source
AI summary
A resistive memory device including: first conductive lines extending in a first direction; second conductive lines extending in a second direction crossing the first direction; and memory cells connected to the first conductive lines and the second conductive lines, wherein the memory cells include: a first memory cell including a first resistive memory layer and a first heating electrode layer, the first heating electrode layer includes a first contact surface in contact with the first resistive memory layer and the first contact surface has a first contact resistance; and a second memory cell including a second resistive memory layer and a second heating electrode layer, the second heating electrode layer includes a second contact surface in contact with the second resistive memory layer and the second contact surface has a second contact resistance different from the first contact resistance.