Resistive Memory Controller Power-Aware Write Scheduling
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Solution Overview
Problem
Current memory systems do not effectively manage power consumption during write operations in resistive memory devices, leading to performance degradation due to differences in power consumption between writing logical high and low data, which are not considered in existing systems.
Innovation Solution
A memory system that schedules write commands based on the number of low bits or high bits in write data, calculating power consumption and cumulatively adding it to determine when to issue commands within an allocated power budget, thereby optimizing the number of write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write commands are issued without considering power consumption, then write operation speed is improved, but power consumption increases beyond allocated budget
Solution Approach 1:
The system dynamically adjusts the issuance of write commands based on real-time power consumption calculations. The memory controller calculates power consumption for each write command based on the number of low bits or high bits in write data, and dynamically schedules command issuance to stay within allocated power budget while maximizing write operation throughput
Solution Approach 2:
The system changes the parameter of write command scheduling by introducing power consumption as a scheduling criterion. Instead of uniformly issuing write commands, the system varies the timing and frequency of write commands based on calculated power consumption values, which depend on the bit composition (low bits vs high bits) of write data
2Reliability
If write commands are scheduled based on power consumption, then power budget management is improved, but write operation performance decreases
Solution Approach 1:
The system performs partial write operations by issuing write commands selectively rather than in full batches. By calculating power consumption for individual write commands and issuing them incrementally within power budget constraints, the system achieves reliable power management while maintaining acceptable write performance through optimized partial execution
3Productivity
If the number of write commands is increased, then write operation throughput is improved, but power consumption exceeds allocated budget
Solution Approach 1:
The system implements feedback control by calculating power consumption for each write command based on write data characteristics (number of low bits or high bits) and using this information to adjust subsequent write command issuance. The memory controller continuously monitors cumulative power consumption and adjusts the number of write commands issued to maintain throughput while staying within power budget
Data Source
AI summary
A memory system includes a memory cell array including a plurality of resistive memory cells; a peripheral circuit suitable for providing a set pulse or a reset pulse with write data into a selected memory cell among the resistive memory cells, based on a write command; and a memory controller suitable for providing the write command with the write data to the peripheral circuit and scheduling the write command based on an amount of power consumption calculated depending on the number of either low bits or high bits in the write data.