Resistive Memory Data Line Control Circuit for High-Speed Read Operations
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Solution Overview
Problem
Semiconductor devices using resistive elements face challenges in high-speed read operations due to large parasitic capacitance in data lines, requiring complex circuit configurations that make it difficult to arrange data line control circuits at short intervals, and there is a need to accurately charge data lines with a read reference signal without changing the resistance value of the resistive memory elements.
Innovation Solution
A semiconductor device with a control circuit comprising a first constant current element, a first transistor, and a second transistor, where the first transistor's gate is coupled to the data line, and the second transistor's gate is coupled to one of the source and drain of the first transistor, allowing for simple configuration and efficient charging of data lines with a read reference signal, enabling high-speed read operations and simultaneous reading of multiple memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single multiplexer is selectively activated for each data line, then the data line control circuit can be simplified, but the data line has large parasitic capacitance requiring large current drive capability
Solution Approach 1:
The data line control circuit is divided into multiple independent circuits, each responsible for controlling a specific data line. This segmentation allows each control circuit to be simpler while collectively managing the parasitic capacitance of all data lines through coordinated operation.
Solution Approach 2:
The control circuit performs preliminary charging of the data line to a reference voltage level before the actual read operation. This preliminary action reduces the capacitive load during the critical read phase, allowing simpler control circuits to operate effectively.
2Speed
If the data line is charged at high speed, then the read operation speed is improved, but the parasitic capacitance requires large current drive capability
Solution Approach 1:
The data line is pre-charged to a reference voltage level before the read operation begins. This preliminary charging action reduces the amount of current needed during the actual read operation, enabling high-speed operation without requiring excessively large current drive capability.
Solution Approach 2:
The control circuit uses feedback mechanisms to monitor the data line voltage and adjust the charging current accordingly. This feedback control enables high-speed charging while optimizing power consumption by supplying current only when and where needed.
3Power
If the read reference signal voltage is increased to acquire larger read current, then the read current is improved, but the resistance value of the resistive memory element may be changed
Solution Approach 1:
The data line is pre-charged to a safe reference voltage level that is known not to exceed the maximum safe voltage for the resistive memory element. This preliminary action ensures that subsequent read operations can proceed at high speeds without risking damage to the memory element's resistance state.
Solution Approach 2:
The control circuit incorporates feedback mechanisms that monitor the voltage levels and current flow during read operations. This feedback control ensures that the read reference signal voltage remains within safe limits while still providing sufficient read current for high-speed operation.
4Productivity
If data line control circuits are arranged at short intervals, then the number of simultaneous read operations is increased, but the circuit configuration becomes complex
Solution Approach 1:
The control system is divided into multiple independent data line control circuits that can be arranged at short intervals. Each circuit is a self-contained module with standardized interfaces, allowing them to be densely packed while maintaining operational independence and simplicity.
Solution Approach 2:
The data line control circuits are designed with universal functionality that allows them to control multiple data lines through time-division or signal-sharing mechanisms. This multi-functionality reduces the need for separate dedicated control circuits for each data line, enabling shorter intervals between control circuits.
Data Source
AI summary
A semiconductor device including: a resistive memory element; a data line electrically coupled to the resistive memory element; a control line; a power supply line; and a control circuit including a first constant current element, a first transistor, and a second transistor. In the control circuit, the first transistor has a gate coupled to the data line, one of a source and a drain coupled to the first constant current element, and the other one of the source and the drain coupled to the power supply line. The second transistor has a gate coupled to one of the source and the drain of the first transistor, one of a source and a drain coupled to the data line, and the other one of the source and the drain coupled to the control line.