Resistive Change Memory Array Layout for DDR-Speed Readout
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Solution Overview
Problem
Current resistive change memory arrays face limitations in achieving high speed and low power operations, making them less compatible with existing DDR architectures, which require efficient reading and programming capabilities.
Innovation Solution
The development of a resistive change element memory array architecture that includes a plurality of word lines, bit lines, select lines, and memory cells with resistive change elements and reference elements, allowing for rapid access and low power consumption through a folded bit line arrangement and sense amplifiers that compare discharge rates to determine informational states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional resistive change memory arrays are used, then manufacturing simplicity is maintained, but reading and programming operations are slow and consume high power
Solution Approach 1:
The memory array is divided into multiple blocks with shared bit lines and sense amplifiers. Each block contains multiple columns of memory cells that share common bit lines, allowing parallel access and reducing the overall time and power required for reading and programming operations across the entire array.
Solution Approach 2:
Multiple columns of memory cells share common bit lines and sense amplifiers. This merging of resources allows the sense amplifiers to efficiently compare discharge rates across multiple cells simultaneously, reducing redundant power consumption and increasing operational speed by handling multiple cells in parallel rather than sequentially.
2Speed
If resistive change memory arrays without reference elements are used, then device complexity is reduced, but reading accuracy and speed are insufficient for DDR architecture compatibility
Solution Approach 1:
Reference elements are introduced as intermediary components between the memory cells and the sense amplifiers. These reference elements provide a baseline for comparison during read operations, enabling the sense amplifiers to accurately determine the state of memory cells by comparing discharge rates. This intermediary structure enables DDR-compatible reading speeds while maintaining a relatively simple overall array architecture.
3Loss of time
If traditional memory array architectures are used, then manufacturing processes are simple, but timing requirements for DDR compatibility are not met
Solution Approach 1:
The memory cells are pre-configured with select lines and reference elements positioned to enable rapid simultaneous activation during read operations. This preliminary arrangement of components allows the array to meet stringent DDR timing requirements by reducing the time needed to activate and compare multiple cells in parallel, without requiring complex external control circuitry.
Solution Approach 2:
The array architecture transitions from a simple two-dimensional grid to a three-dimensional structure with multiple blocks stacked or arranged in layers, sharing bit lines and sense amplifiers. This dimensional change enables more efficient use of space and resources, allowing faster access times and DDR compatibility while keeping the manufacturing process relatively straightforward.
4Use of energy by moving object
If resistive change memory arrays are used without folded bit line arrangement, then device complexity is minimized, but power consumption increases and reading speed decreases
Solution Approach 1:
The folded bit line arrangement creates an asymmetric structure where bit lines are folded back on themselves, allowing multiple memory columns to share common bit lines. This asymmetric configuration reduces the total length of bit lines required, thereby reducing power consumption and capacitive loading, while enabling parallel read operations to improve speed. The complexity increase is localized to the bit line routing rather than the overall array structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture enables faster and more energy-efficient reading and programming operations, enhancing compatibility with DDR memory architectures by reducing timing and power requirements, thus improving the versatility of resistive change memory technology.
Implementation Method 1
each resistive change element has a first terminal and a second terminal, and is capable of being switched between at least two non-volatile resistance values, a first resistance value corresponding to a first informational state and a second resistance value corresponding to a second informational state
Implementation Method 2
the sense amplifier is enabled to compare a discharge rate through the resistive change element to a discharge rate through the reference element
Data Source
AI summary
A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration.