Resistive Change Memory Circuit for DDR-Compatible High-Speed Reads
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Solution Overview
Problem
Current resistive change memory arrays face limitations in achieving high speed and low power operations, making them incompatible with existing DDR memory architectures, which require faster access and lower power consumption.
Innovation Solution
The development of a circuit architecture for resistive change element memory arrays with a DDR-compatible design, featuring a plurality of word lines, bit lines, select lines, and memory cells with resistive change elements that can switch between non-volatile resistance states, along with reference elements and sense amplifiers for efficient reading and programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional resistive change memory arrays are used, then non-volatile storage is achieved, but access speed and power consumption are insufficient for DDR compatibility
Solution Approach 1:
The memory array is segmented into multiple banks, with each bank containing multiple arrays that can be independently accessed. This segmentation allows parallel operations across different banks, increasing overall access speed and enabling DDR-compatible timing requirements to be met while maintaining non-volatile storage capabilities
Solution Approach 2:
The patent implements dynamic control of word lines and bit lines with precise timing sequences that adapt to DDR interface requirements. The memory controller dynamically manages read/write operations, precharging bit lines at appropriate times and controlling word line activation to achieve double data rate timing while maintaining reliable access to resistive change elements
2Speed
If faster access speed is implemented, then DDR compatibility improves, but power consumption increases
Solution Approach 1:
The memory system employs periodic precharging of bit lines and controlled activation of word lines in rhythmic sequences that match DDR timing requirements. This periodic action enables fast access speeds by preparing circuits in advance, while the regular timing patterns allow for optimized power management where circuits are actively driven only during necessary operation windows
Solution Approach 2:
The patent utilizes controlled changes in voltage parameters and current levels during different operation phases. By dynamically adjusting voltage levels on word lines and bit lines based on operation type (read vs. write) and timing phase, the system achieves fast access when needed while minimizing power consumption during idle or less demanding periods
3Adaptability or versatility
If DDR-compatible architecture is implemented, then interface versatility improves, but device complexity increases
Solution Approach 1:
The memory controller is designed with multi-functional capabilities that handle both DDR interface protocols and resistive change element operations through unified control logic. The same control circuitry manages precharging, word line activation, and data sensing for both read and write operations, reducing overall system complexity despite DDR compatibility requirements
Solution Approach 2:
The patent introduces sense amplifiers as intermediary components between the DDR interface and the resistive change memory arrays. These sense amplifiers buffer and condition signals, translating DDR-compatible read/write commands into appropriate voltage and current levels for driving resistive change elements, thereby isolating the complexity of interface protocols from the memory array itself
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture enables rapid access and low-power reading and programming of resistive change memory arrays, overcoming the limitations of existing technologies by allowing for compatibility with DDR memory interfaces, thereby enhancing the versatility and performance of resistive change memory technology.
Implementation Method 1
resistive change element having a first terminal and a second terminal... capable of being adjusted between a non-volatile first resistive state and a non-volatile second resistive state in response to an applied voltage
Implementation Method 2
sense amplifiers... At least one of the plurality of sense amplifiers is capable of comparing a voltage difference between a first bit line and a second bit line
Data Source
AI summary
A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration.