Resistive Memory Deck Region Classification Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Next-generation resistive change memory devices face reliability issues due to read disturbance and cyclic endurance caused by resistance differences between memory cells near and far from the control block, making accurate classification and control of memory cell regions challenging in three-dimensionally arranged memory decks.
Innovation Solution
A semiconductor memory device and system that includes a control circuit block, pattern generation block, position correction block, and bit error determination block to classify memory cells into near, middle, and far regions based on positional factors and bit error ratios, using pattern generation signals and correction codes to generate reset signals for region-specific error determination and adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are classified into near and far regions based on position, then reliability is improved, but device complexity increases
Solution Approach 1:
The memory cell array is segmented into multiple decks (first deck, second deck, etc.) with each deck containing a three-dimensional cross-point array. Control circuit blocks are separately provided for each deck, enabling independent control and classification of memory cells into near and far regions based on their positional relationships with respective control blocks.
Solution Approach 2:
The patent extends the classification from two-dimensional to three-dimensional space by stacking multiple memory decks vertically. Each deck operates with its own control circuit block, creating multiple layers of near and far cell regions in the vertical dimension, thereby managing complexity through spatial distribution.
2Manufacturing precision
If multiple control circuit blocks are provided for multiple memory decks, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The control system is segmented into multiple independent control circuit blocks, each dedicated to a specific memory deck. This segmentation allows precise control of each deck's memory cells without interference, enabling accurate classification and management of near and far cell regions in each deck independently.
Solution Approach 2:
Each control circuit block is designed with universal functionality to manage its associated memory deck, including generating control signals for word lines and bit lines, classifying memory cells into near and far regions, and handling read/write operations. This multi-functional design reduces overall system complexity through standardization.
3Measurement precision
If memory cells are classified into three regions (near, middle, far), then bit error ratio management is improved, but device complexity increases
Solution Approach 1:
Each memory deck is segmented into three distinct regions (near cell region, middle cell region, far cell region) based on the distance from the control circuit block. This segmentation enables precise measurement and management of bit error ratios in each region, allowing differentiated control strategies for each zone.
Solution Approach 2:
Different control strategies and control signals are applied to each region (near, middle, far) based on their specific characteristics. The control circuit block generates region-specific control signals that account for the varying error rates and access patterns in each zone,实现ing localized optimization of memory operations.
Data Source
AI summary
A semiconductor memory device includes a resistive change memory device including a control circuit block and a plurality of memory decks electrically connected with the control circuit block. The semiconductor memory device includes a pattern generation block, a position correction block and a position decision block. The pattern generation block receives a row address, a column address and a deck selection signal to generate a plurality of pattern generation signals to select a plurality of memory cells in the memory deck in various patterns. The position correction block receives a temporary code for classifying the memory cells into a temporary near cell region and a temporary far cell region and for reflecting a position of the memory deck in the temporary code to output a correction code. The position decision block is configured to generate first to third reset signals to reset a near cell region, a middle cell region and a far cell region based on the pattern generation signals and the correction code.