Resistive Memory Reset via Dual Bias Segmentation

The voltage application is segmented into two independent bias sources: a first bias voltage applied to the word line and a second bias voltage applied to the bit line. This segmentation allows each voltage to be independently controlled and optimized, enabling the reset operation to be performed without subjecting the transistor to excessive voltage stress that would cause damage.

The method uses bias voltages applied to control terminals (word line and bit line) as intermediaries to indirectly control the voltage across the resistive switching device. By mediating through these control terminals, the reset operation can be achieved without directly applying high voltage to the transistor channel, thus protecting the transistor while still enabling effective reset of the resistive device.

The gate voltage control is segmented by applying the first bias voltage to the word line connected to the gate terminal, while the second bias voltage is applied to the bit line. This segmentation ensures that the voltage differential across the resistive switching device is sufficient for reset, while the absolute voltage at the gate remains within safe operating limits, preventing switch damage.

The method changes the parameter of gate voltage by applying a controlled first bias voltage to the word line rather than allowing uncontrolled high voltage to appear at the gate. This parameter change ensures the gate voltage remains within the transistor's safe operating range while still achieving the necessary voltage differential across the resistive switching device for effective reset operation.