Resistive Memory Write Latency Reduction via Dual Operation Modes

Solution Overview

Problem

Resistive memory devices, such as phase-change RAM, face significant write latency due to the time required for data read, latching, and comparison operations during the write process, which increases the overall write operation time.

Innovation Solution

Implementing a method that differentiates between a first write operation, which includes a read data evaluation and comparison, and a second write operation, which omits these steps, allowing for a faster write process by using a write active command and a write command to reduce unnecessary programming and enhance write speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a first write operation including read data evaluation and comparison is performed, then data writing accuracy is improved, but write latency increases

Engineering Contradiction:

Improvedata writing accuracyVSAvoidwrite latency

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent segments the write operation into two distinct modes: a first write operation that includes read data evaluation and comparison for high accuracy, and a second write operation that excludes these steps for low latency. This segmentation allows the system to select the appropriate operation mode based on specific requirements, resolving the contradiction between accuracy and speed by providing specialized pathways for each objective.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic operation mode selection between first and second write operations based on system state and requirements. The control circuit dynamically determines which write operation mode to execute, allowing the system to adapt between accuracy-critical and speed-critical scenarios, effectively managing the trade-off between data writing accuracy and write latency.

Inventive Principle:

Principle #15Dynamics

2Reliability

If read data evaluation operation is included in write process, then data integrity is improved, but write operation time increases

Engineering Contradiction:

Improvedata integrityVSAvoidwrite operation time

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent segments the write operation into two distinct modes: a first write operation that includes read data evaluation and comparison for high accuracy, and a second write operation that excludes these steps for low latency. This segmentation allows the system to select the appropriate operation mode based on specific requirements, resolving the contradiction between accuracy and speed by providing specialized pathways for each objective.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the operational parameters of the write process by introducing two different operation modes with different levels of data evaluation. By adjusting the parameter of whether to perform read data evaluation and comparison, the system can optimize between data integrity and write operation time depending on the specific application context.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10629262B2Method of operating resistive memory device capable of reducing write latency

Publication Date: 2020.04.21 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a method of operating a resistive memory device including a memory cell array. The method includes the resistive memory device performing a first write operation in response to an active command and a write command and performing a second write operation in response to a write active command and the write command. The first write operation includes a read data evaluation operation for latching data read from the memory cell array in response to the active command. The second write operation excludes the read data evaluation operation.