Resistive Memory Gate Control for DNN Linear Switching
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Solution Overview
Problem
Current hardware devices for simulating deep neural network (DNN) models are inefficient due to tunable materials not responding linearly or symmetrically to applied electric fields, making them less effective for accelerating DNN training processes.
Innovation Solution
A semiconductor device with a gate structure and resistive switching medium is introduced, featuring a gate electrode that modulates the electric field perpendicular to current flow, enhancing the linear and symmetric behavior of filament growth and contraction, thereby improving the efficiency of DNN model simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If tunable materials are used in resistive devices to simulate neurons, then hardware acceleration for DNN processing is enabled, but the materials do not respond linearly or symmetrically to applied electric fields reducing analog efficiency
Solution Approach 1:
A gate electrode is introduced as an intermediary component between the top and bottom electrodes, coupled to the resistive switching medium through a gate dielectric layer. This gate electrode acts as a mediator that applies an additional electric field to the resistive switching medium, enabling independent control of the electric field distribution and improving the linearity and symmetry of the material's response to applied fields.
Solution Approach 2:
The invention transitions from a conventional two-terminal resistive device to a three-terminal device by adding the gate electrode dimension. This additional terminal provides a new degree of freedom for controlling the electric field in the resistive switching medium, allowing independent modulation of the electric field perpendicular to the current flow direction, thereby achieving better analog behavior.
2Device complexity
If conventional two-terminal resistive devices are used, then device structure is simple, but they lack the ability to modulate electric field perpendicular to current flow reducing analog performance
Solution Approach 1:
The gate electrode is configured to be movable or adjustable relative to the resistive switching medium, allowing dynamic control of the electric field distribution. The gate electrode can be positioned at different locations (e.g., above, below, or within the resistive switching medium) and adjusted to optimize the electric field modulation for different operating conditions, thereby enhancing analog performance.
Solution Approach 2:
The three-terminal device structure provides multi-functionality by enabling both current flow through the resistive switching medium and independent electric field modulation via the gate electrode. This universal structure can perform both digital switching and analog modulation functions, making it suitable for various DNN operations including weight storage, read, and update operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables more efficient acceleration of stochastic training for DNNs by making resistive switching more analog and symmetric, reducing computational time and improving accuracy.
Implementation Method 1
A gate electrode is disposed between the first dielectric layer and the second dielectric layer and contacting the gate structure in a middle portion thereof to modulate an electric field perpendicular to current flow between the top electrode and the bottom electrode
Data Source
AI summary
Semiconductor devices and methods for forming the semiconductor devices include a gate structure disposed between a top electrode and a bottom electrode, the gate structure including a resistive switching medium contacting a first side of the top electrode and a first side of the bottom electrode. A bottom dielectric layer is disposed on the first side of the bottom electrode around the gate structure. A top dielectric layer is disposed on the first side of the top electrode around the gate structure. A gate electrode is disposed between the first dielectric layer and the second dielectric layer and contacting the gate structure in a middle portion thereof to modulate an electric field perpendicular to current flow between the top electrode and the bottom electrode.