Resistive Memory Device Inhibit Voltage Control
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Solution Overview
Problem
Resistive memory devices face issues with increased leakage current in unselected memory cells due to write pulse increments during programming loops, affecting controllability of cell currents in selected memory cells.
Innovation Solution
A resistive memory device with a memory cell array, a write circuit, a voltage detector, and a voltage generation circuit that adjusts inhibit voltages based on node voltage variations to reduce leakage current and improve controllability of cell currents, by generating pulses with increasing amplitude or pulse width and adjusting inhibit voltages accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write pulse amplitude or width is increased to improve programming reliability in selected memory cells, then programming reliability is improved, but leakage current in unselected memory cells increases
Solution Approach 1:
The patent applies different voltage levels to different groups of memory cells based on their selection status. Selected memory cells receive the full write pulse with increased amplitude or width for reliable programming, while unselected memory cells receive inhibited voltages (first inhibit voltage on unselected word lines, second inhibit voltage on unselected bit lines) to suppress leakage current. This local differentiation resolves the contradiction by allowing high write pulses only where needed.
Solution Approach 2:
The patent applies inhibit voltages to unselected word lines and bit lines before the write pulse is applied to prevent leakage current from developing. The first inhibit voltage is applied to unselected word lines and the second inhibit voltage to unselected bit lines in advance, creating a protective potential barrier that counteracts the harmful leakage effect before it can occur during the programming operation.
2Reliability
If write pulse is increased to ensure programming in selected memory cells, then programming completeness is improved, but controllability of cell current deteriorates
Solution Approach 1:
The patent implements precise local control by applying the write pulse only to the selected memory cell while applying inhibit voltages to all unselected memory cells. The write circuit controls the amplitude and width of the write pulse, while the voltage generation circuit independently controls the first inhibit voltage on unselected word lines and the second inhibit voltage on unselected bit lines, enabling fine-grained controllability of currents in different cell groups.
Solution Approach 2:
The patent employs a voltage detector that monitors the node voltage at the connection node between the write circuit and the selected memory cell. This detected voltage information is fed back to the voltage generation circuit, which adjusts the second inhibit voltage level based on the actual voltage conditions. This feedback mechanism enables dynamic adjustment to maintain optimal controllability while ensuring complete programming.
Data Source
AI summary
A resistive memory device includes a memory cell array that has a plurality of resistive memory cells that are arranged respectively on regions where a plurality of first signal lines and a plurality of second signal lines cross each other. A write circuit is connected to a selected first signal line that is connected to a selected memory cell from among the plurality of memory cells, and provides pulses to the selected memory cell. A voltage detector detects a node voltage at a connection node between the selected first signal line and the write circuit. A voltage generation circuit generates a first inhibit voltage and a second inhibit voltage that are applied respectively to unselected first and second signal lines connected to unselected memory cells from among the plurality of memory cells, and changes a voltage level of the second inhibit voltage based on the node voltage that is detected.