Resistive Memory Device Insulator Configuration for Sneak Current Reduction
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Solution Overview
Problem
Conventional resistive random access memory devices face issues with sneak currents and reset operation failures due to strong electric fields and material degradation, particularly in three-dimensional memory cell arrays where the virtual TFT is easily turned on, leading to reliability concerns.
Innovation Solution
The memory device incorporates a first insulator with a lower dielectric constant between the oxide region and the semiconductor region, increasing the distance between the semiconductor region and the bit line, which weakens the electric field and prevents sneak currents, and optionally includes additional oxide or insulator layers to further enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the distance between the semiconductor region and the bit line is reduced to improve integration density, then the memory device achieves higher capacity and miniaturization, but the electric field strength increases causing sneak currents and reset operation failures
Solution Approach 1:
An oxide region is introduced as an intermediary layer between the semiconductor region and the bit line. This oxide region acts as a mediator that modulates the electric field distribution, preventing direct strong interaction between the bit line and semiconductor region that would cause sneak currents and reset failures.
Solution Approach 2:
The dielectric constant of the insulator is changed by selecting materials with different dielectric properties. A first insulator with lower dielectric constant is placed between the oxide region and semiconductor region, while a second insulator with higher dielectric constant is placed between the oxide region and bit line, optimizing electric field distribution to prevent sneak currents while maintaining integration density.
2Speed
If a high dielectric constant material is used between the oxide region and bit line to strengthen field control, then switching performance improves, but sneak currents increase due to excessive field strength in the semiconductor region
Solution Approach 1:
Different insulator materials with different dielectric constants are used in different locations: a lower dielectric constant material between the oxide region and semiconductor region to reduce field strength and prevent sneak currents, and a higher dielectric constant material between the oxide region and bit line to maintain switching performance.
3Ease of manufacture
If the memory cell structure is simplified to reduce manufacturing complexity, then fabrication ease improves, but reliability decreases due to increased susceptibility to material degradation and sneak currents
Solution Approach 1:
The insulator layer is segmented into multiple distinct layers with different dielectric constants: a first insulator layer between the oxide region and semiconductor region, and a second insulator layer between the oxide region and bit line. This segmentation allows independent optimization of each layer's properties to simultaneously achieve manufacturing feasibility and improved reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the reliability of the memory device by reducing sneak currents and preventing material degradation, ensuring stable resistance switching and reliable data storage operations.
Implementation Method 1
increasing the distance between the semiconductor region and the bit line, which weakens the electric field and prevents sneak currents
Implementation Method 2
an electrical resistance changes by changing band structures of titanium oxide and amorphous silicon that acts as a barrier film using modulation of a vacancy density by applying a bias
Data Source
AI summary
A memory device is described. A first conductive layer extends in a first direction. A second conductive layer extends in the first direction. A third conductive layer extends in a second direction intersecting the first direction. A first oxide region is disposed between the first conductive layer and the third conductive layer and between the second conductive layer and the third conductive layer. A semiconductor region is disposed between the first conductive layer and the first oxide region and between the first conductive layer and the second conductive layer. A second distance between the semiconductor region, which is disposed between the first conductive layer and the second conductive layer, and the third conductive layer, is longer than a first distance between the semiconductor region, which is disposed between the first conductive layer and the first oxide region, and the third conductive layer.