Resistive Memory Logic Gate Stacked on Transistor
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Solution Overview
Problem
The miniaturization of integrated circuit (IC) chips faces challenges in increasing product density and reducing costs while maintaining functionality, as conventional logic gates occupy significant surface area and consume high power.
Innovation Solution
The integration of resistive non-volatile memory devices with metal oxide semiconductor transistors in logic gates, where the resistive memory devices are stacked on top of the transistors, allowing for reduced surface area usage and low power consumption, enabling the creation of logic gates that perform OR, NOR, AND, and NAND operations without increasing the chip's surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional logic gates are used, then logic operations can be performed, but surface area consumption is high
Solution Approach 1:
The patent transitions from planar logic gate layouts to a three-dimensional stacked configuration where resistive memory devices are positioned vertically above transistor channels. This vertical stacking enables logic operations to be performed while occupying minimal chip surface area, directly resolving the contradiction between maintaining logic functionality and reducing surface area consumption.
Solution Approach 2:
The patent combines memory and logic functions into a single integrated structure where resistive memory devices serve dual purposes as both storage elements and logic gate components. This merging eliminates the need for separate logic gate circuits, thereby reducing overall surface area while maintaining full logic operational capability.
2Use of energy by moving object
If conventional logic gates are used, then logic operations can be performed, but power consumption is high
Solution Approach 1:
The resistive memory devices inherently retain their resistance states without requiring continuous power supply, enabling logic operations to be performed using only the stored resistance patterns. This self-service characteristic eliminates the need for continuous power consumption associated with conventional logic gate operation, directly resolving the contradiction between power efficiency and logic operation capability.
Solution Approach 2:
The patent replaces the active transistor-based logic gate mechanism with a passive resistive memory-based logic mechanism. Instead of using continuously powered transistors to perform logic operations, the system uses the resistance states of memory devices to represent and process logic values, dramatically reducing power consumption while maintaining logic functionality.
3Area of stationary object
If surface area is reduced for miniaturization, then product density increases, but manufacturing complexity increases
Solution Approach 1:
The resistive memory devices serve multiple functions simultaneously: they act as both storage elements and logic gate components. This multi-functionality means that the same fabrication processes used to create memory devices can also create logic gates, eliminating the need for separate logic gate fabrication and reducing overall manufacturing complexity despite the reduced surface area and stacked configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for increased product density and reduced power consumption, achieving efficient logic operations while maintaining data non-volatility and compatibility with existing fabrication processes, thus addressing the challenges of miniaturization and cost reduction in IC chip development.
Implementation Method 1
a first resistive non-volatile memory device and a second resistive non-volatile memory device... When input voltages having different voltage levels are respectively applied to the first input terminal and the second input terminal, the resistive non-volatile memory devices may have different resistance states
Data Source
AI summary
A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate.