Resistive Memory Device Vertical Pillar Structure
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Solution Overview
Problem
The manufacturing of resistive memory devices with a three-dimensional structure faces challenges in achieving uniform semiconductor oxide film thickness and reproducibility, leading to increased costs and decreased yield due to complex processes.
Innovation Solution
A resistive memory device with a simplified three-dimensional structure is developed, featuring vertical and horizontal components with a memory cell formed at their intersections, comprising a gate insulating film, semiconductor film, and resistive film, where the first and second electrode areas are electrically connected to horizontal components, facilitating easier manufacturing and reduced sneak current formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a three-dimensional structure with physically separated complement resistance memory elements is used to suppress sneak current, then reliability is improved, but manufacturing complexity increases and yield decreases due to the difficulty of forming uniform semiconductor oxide films
Solution Approach 1:
The memory cell is divided into distinct functional regions: a gate insulating film region formed on the vertical component surface, a semiconductor film region formed on the gate insulating film, and a resistive film region formed on the semiconductor film. This segmentation allows each region to be optimized independently, with the gate insulating film providing electrical isolation to suppress sneak current while the semiconductor and resistive films are formed through simpler sequential processes rather than requiring precise control of thick oxide films.
Solution Approach 2:
The invention transitions from a planar two-dimensional layout to a three-dimensional vertical structure. The vertical components extend in the vertical direction from the substrate surface, with gate insulating films, semiconductor films, and resistive films formed in sequential layers. This vertical stacking enables high integration density while using simpler thin film formation processes compared to planar approaches that require thick uniform oxide films.
2Reliability
If a three-dimensional structure with physically separated complement resistance memory elements is used to suppress sneak current, then reliability is improved, but manufacturing precision requirements increase due to the need for uniform film thickness
Solution Approach 1:
The memory cell is divided into distinct functional regions: a gate insulating film region formed on the vertical component surface, a semiconductor film region formed on the gate insulating film, and a resistive film region formed on the semiconductor film. This segmentation allows each region to be optimized independently, with the gate insulating film providing electrical isolation to suppress sneak current while the semiconductor and resistive films are formed through simpler sequential processes rather than requiring precise control of thick oxide films.
Solution Approach 2:
The invention changes the material parameters and film thicknesses to achieve the desired functionality. Instead of using thick semiconductor oxide films (tens to hundreds of nanometers) that require precise thickness control, the invention uses thin gate insulating films (a few nanometers) formed by atomic layer deposition or chemical vapor deposition, followed by thin semiconductor and resistive films. This parameter change reduces the manufacturing precision requirements while maintaining sneak current suppression through the gate insulating film's electrical isolation properties.
3Reliability
If a three-dimensional structure with physically separated complement resistance memory elements is used to suppress sneak current, then reliability is improved, but device complexity increases due to multiple film layers and formation steps
Solution Approach 1:
The invention merges multiple functions into a unified vertical structure. The vertical components serve as both bit lines and structural support, while the gate insulating film, semiconductor film, and resistive film are combined in a sequential stack that forms the complete memory cell. This merging eliminates the need for separate physical isolation structures required in conventional designs, reducing overall device complexity while maintaining sneak current suppression through the gate insulating film's electrical isolation.
Solution Approach 2:
The invention transitions from a planar two-dimensional layout to a three-dimensional vertical structure. The vertical components extend in the vertical direction from the substrate surface, with gate insulating films, semiconductor films, and resistive films formed in sequential layers. This vertical stacking enables high integration density while using simpler thin film formation processes compared to planar approaches that require thick uniform oxide films.
Data Source
AI summary
Provide a resistive random-access memory device having an optimized 3D construction. A resistive random-access memory includes a plurality of pillars, a plurality of bit lines, and a memory cell. The pillars extend vertically along the main surface of the substrate. The bit lines extend in a horizontal direction. The memory cell is formed at the intersection of the pillars and the bit lines. The memory cell includes a gate insulating film, a semiconductor film, and a resistive element. The gate insulating film is formed on the circumference of the pillar. The semiconductor film is formed on the circumference of gate insulating film and provides a channel area. The resistive element is formed on the circumference of the semiconductor film. A first electrode area on the circumference of the resistive element and a second electrode area facing the first electrode area are electrically connected to a pair of adjacent bit lines.