Resistive Memory Array Reference-Line Readout for DDR Speed
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Solution Overview
Problem
Current resistive change memory arrays face limitations in achieving high speed and low power operations, making them less compatible with existing DDR architectures, which require efficient reading and programming capabilities.
Innovation Solution
The development of a DDR-compatible resistive change element memory array architecture that includes a plurality of word lines, bit lines, select lines, memory cells with resistive change elements, reference elements, and sense amplifiers, allowing for rapid access and low power consumption through a folded bit line arrangement and reference resistor-based discharge comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional resistive change memory arrays are used, then manufacturing simplicity is maintained, but reading and programming speed is insufficient for DDR architecture compatibility
Solution Approach 1:
The memory array is segmented into multiple bit line groups, each group containing a subset of bit lines that can be independently activated. This segmentation allows parallel reading and programming operations across different bit line groups, thereby increasing overall access speed while maintaining manageable complexity through modular organization
Solution Approach 2:
The patent introduces select lines as an additional dimension for addressing memory cells, creating a multi-dimensional access structure beyond traditional row-column organization. This enables more efficient cell selection and facilitates faster parallel operations by providing multiple pathways to access memory elements simultaneously
2Speed
If high speed operations are implemented, then DDR compatibility improves, but power consumption increases
Solution Approach 1:
The memory array implements local quality by assigning different operational characteristics to different regions. Specifically, certain bit line groups are configured for high-speed reading operations while others are optimized for programming, allowing the system to achieve high speed where needed without incurring power penalties across the entire array
Solution Approach 2:
The patent employs periodic switching of bit line groups between active and inactive states during reading and programming operations. By activating only the necessary bit line groups at specific time intervals rather than continuously, the system achieves high-speed operations when required while reducing overall power consumption through periodic rather than continuous operation
3Speed
If reference elements are added for rapid reading, then reading speed improves, but device complexity increases
Solution Approach 1:
The reference elements serve multiple functions: they provide reference currents for rapid reading operations, enable differential sensing to improve signal detection, and facilitate quick state determination without requiring additional complex circuitry. This multi-functionality allows reading speed improvement while minimizing the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture enables rapid reading and programming of resistive change memory arrays with reduced power consumption, enhancing compatibility with DDR architectures and improving overall performance.
Implementation Method 1
each resistive change element having a first terminal and a second terminal, the first terminal of each resistive change element being in electrical communication with a select line, and each resistive change element switchable between at least two non-volatile resistance values in response to an applied electrical stimulus
Implementation Method 2
comparing the rate of discharge through the resistive change element to the rate of discharge through the reference element, wherein a greater rate of discharge through the resistive change element corresponds to a first informational state being stored within the resistive change element and a greater rate of discharge through the reference element corresponds to a second informational state being stored within the resistive change element
Data Source
AI summary
A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration.