Resistive Memory Cell Resistance Adjustment for Overshoot Reduction
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Solution Overview
Problem
Resistive memory devices face challenges in maintaining performance and endurance due to overshoot issues near access points, which degrade their operational efficiency and reliability.
Innovation Solution
The resistive memory device adjusts the resistance value of selected memory cells based on their distance from the access point by controlling the voltage levels applied to row and column selection switches, thereby reducing overshoot and enhancing performance and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform resistance is applied to all memory cells, then device complexity is reduced, but performance and endurance degrade due to overshoot issues near access points
Solution Approach 1:
The patent applies different resistance values to different regions of the memory cell array based on their distance from access points. Memory cells closer to access points experience different resistance than those farther away, creating local quality variations that compensate for position-dependent overshoot effects and improve overall reliability
Solution Approach 2:
The patent dynamically changes the resistance parameter of memory cells based on their position in the array. By adjusting resistance values according to distance from access points, the system optimizes performance and endurance without requiring complete redesign of the memory architecture
2Reliability
If resistance is adjusted based on distance from access point, then overshoot is reduced and performance improves, but device complexity increases due to additional control circuitry
Solution Approach 1:
The control circuit pre-calculates and applies appropriate resistance values to memory cells before write operations based on their known positions in the array. This preliminary adjustment prevents overshoot issues before they occur, improving operational efficiency without requiring complex real-time adjustments during operation
Solution Approach 2:
The patent introduces a control circuit as an intermediary between the write/read circuit and memory cells. This intermediary calculates position-based resistance values and applies them through selection switches, managing the complexity in a centralized manner rather than requiring distributed complexity across all memory cells
Data Source
AI summary
A resistive memory includes a memory cell array, a write/read circuitry and a control circuitry. The memory cell array includes a plurality of resistive memory cells coupled to a plurality of word-lines and a plurality of bit-lines. The write/read circuitry is coupled to the memory cell array through a row decoder and a column decoder, the write/read circuitry performs a write operation to write write data in a target page of the memory cell array, and verifies the write operation by comparing read data read from the target page with the write data. The control circuitry controls at least one of the row decoder, the column decoder and the write/read circuitry to control a resistance which a selected memory cell experiences according to a distance from an access point to the selected memory cell in the memory cell array based on an address.