Resistive Memory Self-Aligned Scaling and Speed
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Solution Overview
Problem
Conventional resistive memory devices face challenges in scaling down due to the limitations of the metal oxide and upper electrode layer patterning process, which hinders the miniaturization of semiconductor devices and affects programming/erasing speed.
Innovation Solution
A resistive memory device with a semiconductor substrate, dielectric layer, and metal electrode layer is fabricated using a self-aligned structure that eliminates the need for additional photolithography/etching processes, allowing for proportional scaling with critical dimension shrinkage and enhancing the program/erase speed through a corner effect created by the insulating layer in the recess.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional photolithography/etching processes are used to pattern the metal oxide layer and upper electrode layer, then current leakage is avoided, but the metal oxide layer and upper electrode layer cannot be scaled down proportionally with critical dimension shrinkage
Solution Approach 1:
The patent merges the formation of the insulating layer and metal electrode layer into a single self-aligned structure. The insulating layer is formed first, then the metal electrode layer is deposited conformally on top of it, eliminating the need for separate photolithography and etching steps. This integrated approach allows both layers to scale down proportionally while maintaining current leakage prevention through the self-aligned configuration where the insulating layer completely covers the lower electrode layer.
Solution Approach 2:
The insulating layer is formed in advance before the metal electrode layer is deposited. This preliminary formation of the insulating layer with proper patterning allows subsequent conformal deposition of the metal electrode layer without requiring additional photolithography steps. The preliminary insulating layer structure pre-establishes the alignment necessary to prevent current leakage while enabling scaling.
2Manufacturing precision
If conventional patterning processes are used for metal oxide and upper electrode layers, then manufacturing precision is maintained, but device complexity increases due to additional process steps
Solution Approach 1:
The insulating layer serves itself as the alignment reference for the metal electrode layer through conformal deposition. The metal electrode layer automatically aligns with the insulating layer's pattern without requiring separate photolithography alignment processes. This self-aligned approach maintains manufacturing precision while eliminating complex multi-step patterning processes, thereby reducing fabrication process complexity.
3Reliability
If the metal oxide layer entirely covers the lower electrode layer to prevent current leakage, then reliability is improved, but the additional photolithography/etching process increases manufacturing time
Solution Approach 1:
The patent combines the formation of the insulating layer and metal electrode layer into an integrated self-aligned process. The insulating layer is formed with the necessary coverage to prevent current leakage, and the metal electrode layer is then deposited conformally in a continuous process flow. This merging eliminates the need for separate photolithography and etching steps, reducing fabrication process time while maintaining reliable current leakage prevention through the self-aligned structure.
Data Source
AI summary
A resistive memory includes a semiconductor substrate, a dielectric layer, an insulating layer and a metal electrode layer. The semiconductor substrate has a top surface and a recess extending downwards into the semiconductor substrate from the top surface. The dielectric layer is disposed on the semiconductor substrate and has a first through-hole aligning the recess. The insulating layer is disposed in the first through-hole and the recess. The metal electrode layer is disposed on the insulating layer by which the metal electrode layer is isolated from the semiconductor substrate.