Resistive Memory Device with Shared Column Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Resistive memory devices, such as those using e-fuses, face challenges in maintaining data reliability due to errors caused by the destruction of gate oxides, which can lead to unstable data storage and recognition, especially in applications like DRAM and flash memory where reliability is critical.
Innovation Solution
The implementation of a resistive memory device with two cell arrays and two error correction cell arrays that share column lines, allowing for simultaneous programming and reading of data and error correction codes, thereby increasing data reliability through dual storage and correction mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single cell array is used for data storage, then device complexity is reduced, but data reliability deteriorates due to errors from gate oxide destruction
Solution Approach 1:
The memory device is divided into multiple cell arrays (first cell array, second cell array, first error correction cell array, second error correction cell array) that share column lines. Each array stores specific data or error correction codes independently, allowing parallel operation and redundancy. This segmentation enables simultaneous programming and reading operations across different arrays while maintaining low complexity through shared resources.
Solution Approach 2:
The patent implements copying by storing the same data in both the first and second cell arrays, as well as storing error correction codes in separate error correction cell arrays. This copying mechanism provides redundancy and allows error detection/correction without requiring additional complex verification circuits, as the identical copies can be compared to detect and correct errors.
2Area of stationary object
If multiple cell arrays share column lines, then device area is reduced, but programming and reading operations become more complex
Solution Approach 1:
Multiple cell arrays (first and second cell arrays, plus error correction cell arrays) share common column lines, merging their storage functions into a unified structure. This merging reduces the overall device area by eliminating redundant column lines while enabling simultaneous programming and reading operations across different arrays through coordinated control of row lines and column lines.
Solution Approach 2:
The shared column lines serve multiple functions: they can be used for programming operations in the first cell array, reading operations in the second cell array, storing error correction codes in the error correction cell arrays, and performing error detection/correction operations. This multi-functionality reduces the need for dedicated lines for each operation, simplifying the overall device structure.
3Reliability
If error correction codes are stored separately, then data reliability is improved, but device complexity increases
Solution Approach 1:
The error correction function is segmented into separate first and second error correction cell arrays that are distinct from the main data storage arrays. These dedicated arrays store error correction codes independently, allowing specialized error correction operations without interfering with data storage operations. The segmentation enables parallel processing of data and error correction functions.
Solution Approach 2:
The error correction cell arrays act as intermediaries between the data storage arrays and the error detection/correction logic. These intermediate arrays store the error correction codes that are used to detect and correct errors in the data, providing a dedicated interface for error correction operations without complicating the main data storage structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances data reliability by allowing errors to be detected and corrected, ensuring stable data storage and recognition across the memory device.
Implementation Method 1
An e-fuse stores a data by using a transistor and changing resistance between a gate and a drain/source to the transistor
Implementation Method 2
When a high power supply voltage having such a voltage level that the transistor T may not bear is applied to the gate G, a gate oxide of the transistor T is destroyed to cause the coupling between the gate G and the drain/source D/S
Data Source
AI summary
A resistive memory device includes a first cell array configured to store data, a second cell array configured to share column lines of the first cell array, a first error correction cell array configured to store an error correction code that corresponds to the data to be stored in the first cell array, and a second error correction cell array configured to share column lines of the first error correction cell array.