Resistive Memory Side Barriers for Data Retention
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Solution Overview
Problem
Current memory technologies, such as DRAM and NAND Flash, face limitations in speed, endurance, and cost, with a gap between volatile and non-volatile memory solutions that is not effectively addressed, necessitating a new non-volatile memory with attributes closer to DRAM's speed and endurance while maintaining a cost per gigabyte similar to NAND Flash.
Innovation Solution
A nonvolatile memory device with a heterojunction memory structure comprising a memory layer with variable resistance, a conductive top electrode, and a retention layer with variable ionic conductivity, configured to selectively resist ionic conduction, along with barrier layers to confine ions and vacancies, enhancing data retention and speed without the need for error correction codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used for high-speed memory, then speed and endurance are improved, but cost increases and retention deteriorates
Solution Approach 1:
The memory device is segmented into distinct functional layers: a memory layer for data storage, a retention layer for maintaining data state, and barrier layers for confinement. This segmentation allows each layer to be optimized independently - the memory layer for speed and the retention layer for data retention, resolving the contradiction between these two parameters.
Solution Approach 2:
The patent employs composite heterostructures combining different oxide materials (e.g., HfO2, TiO2, SrRuO3) with distinct properties. The memory layer uses materials with variable resistance, while the retention layer uses materials with controlled ionic conductivity. This composite approach enables simultaneous achievement of high speed (through low-resistance pathways) and high retention (through ionic blocking), directly resolving the DRAM limitation.
2Reliability
If NAND Flash is used for non-volatile storage, then retention and cost are improved, but speed and endurance deteriorate
Solution Approach 1:
The retention layer acts as an intermediary between the memory layer and the top electrode. It mediates the conflicting requirements by allowing electrical conduction for fast write operations while blocking ionic diffusion for long-term data retention. This intermediary structure enables NAND Flash-like retention without sacrificing DRAM-like speed.
Solution Approach 2:
The patent changes the conductivity parameter of the retention layer by controlling oxygen vacancy concentration and ionic conductivity. By adjusting these parameters, the retention layer can switch between allowing ion transport during write operations and blocking ions during data retention, thereby achieving both high speed and high retention simultaneously.
3Reliability
If barrier layers are added to confine ions, then data retention is improved, but device complexity increases
Solution Approach 1:
The barrier layers are merged with the existing memory stack structure rather than being added as separate external components. The bottom barrier layer is integrated at the interface between the template layer and memory layer, while the top barrier layer is integrated at the memory layer-top electrode interface. This merging approach provides effective ion confinement without proportionally increasing device complexity.
Solution Approach 2:
The patent transitions from 2D planar memory structures to 3D vertically-stacked heterostructures. By stacking multiple functional layers (template layer, memory layer, retention layer, barrier layers) in the vertical dimension, the device achieves enhanced data retention through improved ion confinement while maintaining a compact footprint, effectively managing complexity through spatial organization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed memory device achieves high endurance and speed comparable to DRAM while reducing costs, with improved data retention and reliability, enabling efficient storage solutions for mobile devices and cloud data centers without the need for error correction codes, thus bridging the gap between DRAM and NAND Flash.
Implementation Method 1
the retention layer has a variable ionic conductivity, where the retention layer is configured to selectively resist ionic conduction
Implementation Method 2
barrier layers to confine ions and vacancies, enhancing data retention and speed
Implementation Method 3
the memory layer has a variable resistance
Data Source
AI summary
A memory device is disclosed. The memory device includes a bottom contact, and a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a lateral barrier layer connected to the bottom contact, the memory layer, and the conductive top electrode, where the lateral barrier layer is configured to substantially prevent conduction of ions or vacancies from the bottom contact, the memory layer, and the conductive top electrode to the lateral barrier layer.