Resistive-Rail Latch Circuit for Low-Power Single-Phase Clocking
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Solution Overview
Problem
Latch circuits, particularly flip-flops, experience significant power consumption due to redundant transitions of internal nodes when input and output states are the same, contributing to around 50% of total power consumption, and existing low-power techniques either fail to adequately address this or introduce additional power consumption and design complexities.
Innovation Solution
A latch circuit design featuring a master-slave cross-coupled inverter pair configuration where the slave circuit's inverters are coupled to voltage rails through resistive elements, eliminating the need for an internal clock-buffer and enabling single-phase clocking, thereby reducing power consumption and avoiding hold time issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock gating is used to reduce power consumption, then power consumption is reduced for inactive portions, but it is ineffective when data sampled by the clocked element is the same for two consecutive cycles
Solution Approach 1:
The patent implements feedback by comparing the current input data with the previously latched output data. The D input is compared with the Q output from the previous cycle, and this comparison result controls whether the clock signal is enabled. This feedback mechanism detects when data has changed and only allows clocking when necessary, preventing redundant transitions and reducing power consumption while maintaining reliability.
2Loss of energy
If XOR gate and AND gate are added to implement clock on demand, then redundant transitions are avoided, but power consumption increases during regular operation by 23%
Solution Approach 1:
The patent extracts the clock buffer functionality from the critical path and replaces it with a simpler gating mechanism. Instead of using an AND gate to buffer the clock signal (which consumes power during regular operation), the invention directly gates the clock signal based on the data comparison result. This removes the unnecessary power consumption of the clock buffer while still achieving the goal of avoiding redundant transitions.
3Use of energy by moving object
If pulsed clock is generated by AND operation to avoid redundant transitions, then power consumption is reduced, but hold time degradation occurs especially for scan test circuits
Solution Approach 1:
The patent inverts the conventional approach by using a transparent latch during the clock high phase instead of a pulsed clock during the clock low phase. The latch is transparent when the clock is high, allowing data to pass through, and opaque when the clock is low, holding the data. This inversion maintains proper hold time characteristics while still reducing power consumption by controlling the clock signal based on data changes.
4Reliability
If delay cells are inserted to fix hold time violations in scan chains, then hold time is improved, but design complexity and power consumption increase
Solution Approach 1:
The patent applies preliminary action by ensuring that data is fully captured in the master latch before the clock transitions low. The transparent phase is sufficiently long to allow complete data propagation, and the comparison logic is set up in advance to detect when data has changed. This preliminary preparation eliminates the need for additional delay cells in scan chains, reducing both design complexity and power consumption while maintaining hold time requirements.
Data Source
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AI summary
A latch circuit is based on a master-slave cross-coupled inverter pair (40) configuration. The inverters (0, 62) of the slave circuit (42) are coupled to a high voltage rail and a low voltage rail, wherein for each of the two inverters of the slave circuit inverter pair, the coupling to one of the voltage rails is through a resistive element (64, 66). This circuit design avoids the need for an internal clock-buffer and enables single phase clocking (CK), and therefore does not need internal clock signal inversion. The circuit can be implemented with low power, with no dynamic power consumption for redundant transitions when the input (DIN) and the output data signal (DOUT) is same.