Resistor Sheet Resistance Matching via Mask Algorithm
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Solution Overview
Problem
In semiconductor manufacturing, achieving consistent sheet resistance values for high precision resistors across different foundries is challenging due to process technology variations, often requiring additional masking operations, which increases manufacturing complexity and cost.
Innovation Solution
A method involving a semiconductor layout design with a resistor marker layer and a mask generating algorithm to adjust resistor structures, such as width, length, or ion implantation, to match the desired sheet resistance, reducing the need for extra masks and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional masking operations are performed to adjust implant dosage for desired sheet resistance, then sheet resistance precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies preliminary action by pre-calculating the sheet resistance mismatch between different foundries during the design phase. The system estimates the resultant sheet resistance based on known foundry process parameters and proactively determines the required implant dosage adjustment before manufacturing begins. This eliminates the need for additional masking operations during production, as the design is already optimized for the target foundry's process characteristics.
Solution Approach 2:
The patent implements parameter changes by modifying the ion implantation dosage parameter in the resistor structure design. Instead of adding masking operations to adjust sheet resistance, the system changes the implant dosage parameter during design to compensate for foundry-specific process variations. This parameter adjustment achieves the desired sheet resistance precision while maintaining manufacturing simplicity.
2Manufacturing precision
If extra masking operations are added to achieve desired sheet resistance, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The system performs preliminary calculation of sheet resistance mismatch and determines the optimal implant dosage adjustment during the design phase. This advance preparation eliminates the need for time-consuming additional masking operations during manufacturing, thereby maintaining high productivity while achieving the required sheet resistance precision.
3Manufacturing precision
If design is optimized for one foundry's process, then manufacturing precision is improved, but adaptability to other foundries decreases
Solution Approach 1:
The patent enables adaptability across different foundries by implementing parameter changes in the resistor design based on the target foundry's process characteristics. The system calculates the sheet resistance mismatch for different foundries and adjusts the implant dosage parameter accordingly. This allows the same design to achieve consistent sheet resistance precision across multiple foundries without requiring additional masking operations, thereby maintaining both precision and adaptability.
Solution Approach 2:
The patent achieves universality by creating a design system that can adapt to multiple foundries' processes through parameter adjustment. The resistor structure design with modified implant dosage serves multiple functions: it maintains sheet resistance precision for the target foundry while also enabling portability to other foundries. This multi-functional design eliminates the need for foundry-specific masking operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent sheet resistance values within design tolerances, reducing process complexity, cost, and improving yield, while enhancing memory chip portability between foundries.
Implementation Method 1
A sheet resistance matching estimate is performed to ascertain a difference between the baseline sheet resistance and a resultant sheet resistance if the resistor structure were to be manufactured using a manufacturing process. A mask generating algorithm is generated based on the difference effective to achieve a sheet resistance of the resistor structure that is closer to the baseline sheet resistance
Data Source
AI summary
Techniques create a semiconductor layout comprising a resistor structure having a defined baseline sheet resistance. The semiconductor layout includes a resistor marker layer over the resistor structure. A sheet resistance matching estimate is performed to ascertain a difference between the baseline sheet resistance and a resultant sheet resistance if the resistor structure were to be manufactured using a manufacturing process. A mask generating algorithm is generated based on the difference effective to achieve a sheet resistance of the resistor structure that is closer to the baseline sheet resistance rather than the resultant sheet resistance. The mask generating algorithm enables one or more masks to be generated to modify the resistor structure relative to the resistor marker layer.


