Resonant Clock Driver Pulse Control for Frequency Scaling
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Solution Overview
Problem
High power consumption in high-performance digital circuits due to large parasitic capacitance in clock networks, and existing pulse drive systems face issues with efficiency, jitter, process variation, duty cycle control, and voltage scaling.
Innovation Solution
A pulse-mode drive system using a non-inverting delay chain with OR and AND gates to generate pulse control signals for P-channel and N-channel transistors, where the delay chain output determines the asserting edge of the pulses, allowing for efficient resonant clock operation, robustness to process variation, and duty cycle tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional clock distribution networks are used in high-performance digital circuits, then clock signal can be distributed, but power consumption increases significantly due to large parasitic capacitance
Solution Approach 1:
The patent implements periodic switching action by using pulse control signals that are periodically asserted and de-asserted based on clock edges. The first transistor is activated on the rising edge and the second transistor on the falling edge, creating periodic charge/discharge cycles that reduce average power consumption compared to continuous driving of the clock network.
Solution Approach 2:
The patent changes the operational parameters of the clock driver by using dynamic control of transistor switching based on clock edges. The pulse control signals modify the duty cycle and timing parameters, allowing the driver to operate more efficiently by only actively driving during necessary transitions rather than continuously charging parasitic capacitance.
2Loss of energy
If pulse drive systems are used to reduce power consumption, then energy efficiency improves, but jitter and sensitivity to process variation increase
Solution Approach 1:
The patent employs edge-triggered feedback mechanisms where the clock signal edges directly control the assertion of pulse control signals. The rising edge triggers the first transistor and the falling edge triggers the second transistor, creating a feedback loop that automatically adjusts timing based on actual clock signal conditions, thereby reducing jitter and improving robustness to process variation.
Solution Approach 2:
The delay circuits generate pulse control signals in advance of the actual switching event. By predicting the timing based on clock edges and asserting control signals beforehand, the system prepares the transistors for optimal switching, reducing uncertainty and improving timing precision despite process variations.
3Productivity
If frequency scaling is implemented to improve performance, then processing speed increases, but power consumption and duty cycle control issues worsen
Solution Approach 1:
The patent implements dynamic frequency scaling by allowing the clock driver to operate at different frequencies while maintaining optimal duty cycle through edge-triggered control. The system dynamically adjusts its operation based on the input clock frequency, enabling frequency scaling for performance improvement while the periodic pulse control maintains efficient power usage across different operating frequencies.
Solution Approach 2:
The clock driver circuit is designed with universal functionality to operate across a wide range of frequencies and duty cycles. The edge-triggered architecture with complementary transistors allows the same circuit to efficiently drive the clock network at various frequencies, making the system adaptable to different performance requirements without requiring separate optimized circuits for each frequency range.
Data Source
AI summary
A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal.