Resonant Converter Controller Timing Synchronization

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Solution Overview

Problem

Resonant switched-mode power converters face challenges in providing suitable timing control for secondary-side synchronous rectifiers relative to primary-side power switches, affecting power conversion efficiency.

Innovation Solution

A controller with an oscillator, advance timing generator, and dead zone generator is used to generate timing signals for secondary-side synchronous rectifiers, ensuring proper synchronization and adjustment of switching frequencies to optimize power conversion efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If conventional timing control methods are used for secondary-side synchronous rectifiers, then device complexity is reduced, but power conversion efficiency deteriorates due to improper timing synchronization between primary-side and secondary-side switches

Engineering Contradiction:
Improvepower conversion efficiencyVSAvoidcontroller circuit complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The oscillator generates a freeze signal in advance during dead zones to preemptively prevent phase accumulation, ensuring that the secondary-side synchronous rectifier is properly timed relative to the primary-side power switches before the switching event occurs. This preliminary timing control resolves the synchronization issue without requiring complex feedback mechanisms.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The freeze signal acts as an intermediary mechanism between the dead zone generator and the oscillator phase accumulation process. By introducing this intermediate control signal, the patent achieves precise timing synchronization between primary and secondary switches without directly complexifying the overall controller architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If the oscillator continuously accumulates phase during dead zones, then timing precision is maintained, but harmful effects occur due to improper synchronization of secondary-side rectifier timing

Engineering Contradiction:
Improvetiming precisionVSAvoidimproper synchronization effects
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The freeze signal applies preliminary anti-action by preventing phase accumulation during dead zones when improper synchronization would occur. This counter-action is taken in advance to offset the harmful synchronization effects before they can manifest, ensuring proper timing between primary and secondary switches.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

By freezing the oscillator phase during dead zones before secondary-side switching events, the system preemptively establishes correct timing relationships, preventing synchronization errors rather than correcting them after they occur.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8665611B2Controller for a resonant switched-mode power converter
Publication Date: 2014.03.04 INFINEON TECHNOLOGIES AG
  • US8665611B2 patent drawing
  • US8665611B2 patent drawing
  • US8665611B2 patent drawing

AI summary

In accordance with an embodiment, a switch controller for a switched-mode power supply includes an oscillator, an advance timing generator, and a dead zone generator. The advance timing generator generates an advance timing output pulse having a first pulse width that is asserted when the oscillator reaches a first phase. The dead zone generator produces a dead zone output having a second pulse width when the advance timing output pulse is de-asserted. This dead zone output pulse is coupled to a freeze input of the oscillator that freezes the phase accumulation of the oscillator when asserted. The controller also has a primary switch logic circuit that produces primary switch drive signals having a dead zone coincident with the dead zone output, and a secondary switch logic circuit that generates a secondary switch drive signal that is de-asserted when the advance timing output pulse becomes asserted.