Resonant High-Speed Phase Detector for Parasitic Tail Capacitance
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Solution Overview
Problem
High-performance digital to analog converters (DACs) and analog to digital converters (ADCs) face challenges in maintaining timing accuracy at high sampling rates due to parasitic capacitances that limit impedance at the tail node, especially at frequencies in the tens of gigahertz, leading to performance degradation.
Innovation Solution
The use of series inductors tuned to specific clock frequencies to resonate out parasitic capacitances, creating a high impedance current source that maintains accurate phase detection, particularly at frequencies of 10 GHz to 500 GHz, by replacing MOS-based current sources with inductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If MOS-based current sources are used in the phase detector, then the circuit can operate at high frequencies, but parasitic capacitances limit the impedance at the tail node causing performance degradation
Solution Approach 1:
The patent converts the harmful parasitic capacitance into a beneficial element by introducing inductors that resonate with the parasitic capacitance at specific clock frequencies. This resonance creates a high-impedance current source that actually utilizes the previously harmful parasitic capacitance to achieve the desired high impedance, thereby improving timing accuracy while maintaining high-frequency operation
Solution Approach 2:
The patent changes the impedance characteristics of the current source by introducing inductors with specific inductance values that are tuned to resonate with the parasitic capacitance at the clock frequencies. This parameter adjustment transforms the low-impedance MOS current source into a high-impedance resonant current source, resolving the contradiction between high-speed operation and timing accuracy
2Measurement precision
If the impedance at the tail node is increased to improve phase detection accuracy, then timing accuracy improves, but parasitic capacitances prevent achieving high impedance at tens of gigahertz frequencies
Solution Approach 1:
The patent transforms the harmful parasitic capacitance into a useful component by designing inductors that resonate with it at the operating frequencies. This resonance creates the desired high impedance condition for accurate phase detection, effectively converting the harmful parasitic effect into a beneficial resonant behavior
Solution Approach 2:
The patent employs electrical resonance analogous to mechanical vibration, where inductors and parasitic capacitances form resonant circuits that oscillate at specific frequencies. This resonance creates high impedance at the tail node at the clock frequencies, enabling accurate phase detection despite the presence of parasitic capacitances
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the phase detector's performance by maintaining a high impedance at critical frequencies, reducing parasitic capacitance effects and improving timing accuracy in high-speed converters.
Implementation Method 1
the first inductor and the second inductor form a resonant circuit that resonates at a frequency of the first clock signal and the second clock signal
Implementation Method 2
the first inductor and the second inductor form a resonant circuit that resonates at a frequency of the first clock signal and the second clock signal
Data Source
AI summary
In one embodiment, the disclosure relates to a phase detector. The phase detector may include a first inductor having an inductance L1; a second inductor having an inductance L2; and a frequency mixer having a parasitic capacitance CTail, the frequency mixer comprising, a common node tail; a first clock signal generator configured to output a first clock signal having a first frequency, a second clock signal generator configured to output a second clock signal having a second frequency, the first clock signal generator and the second clock signal generator in electrical communication with the common node tail, a first resistor in electrical communication with the first clock signal generator, a second resistor in electrical communication with the second clock signal generator, and an output channel configured to transmit a DC voltage signal (Vphase) that corresponds to the phase relationship between the first clock signal and the second clock signal.