Resonator Through-Electrode Structure for Etching Damage Control
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Solution Overview
Problem
The existing method for forming through electrodes in semiconductor substrates using wet etching leads to isotropic etching, causing side etching and unintended metal material entry, resulting in wiring pattern failures.
Innovation Solution
A method involving dry etching to form through holes in the semiconductor substrate and wet etching to penetrate the insulating layer, with annular metal layers acting as guard rings to restrict side etching and prevent plasma damage to wiring layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wet etching is used to form through holes in the insulating layer, then the through holes can be formed effectively, but side etching occurs causing wiring pattern failure
Solution Approach 1:
An annular metal layer is introduced as an intermediary component between the through electrode and the insulating layer. This metal layer acts as a barrier that prevents the etching solution from laterally eroding the insulating layer and damaging the wiring patterns, thereby enabling the use of wet etching without causing side etching damage.
Solution Approach 2:
The annular metal layer is formed in advance before the through hole etching process. This preliminary action creates a protective structure that prevents side etching from occurring during the subsequent wet etching of the insulating layer, thus preserving wiring pattern integrity before the harmful effect can manifest.
2Manufacturing precision
If dry etching is used to penetrate the semiconductor substrate, then high aspect ratio through holes can be formed, but plasma damage may occur to the wiring layer
Solution Approach 1:
The etching process is segmented into two distinct stages: first, dry etching is used to penetrate the semiconductor substrate to form high aspect ratio holes; second, wet etching is used to penetrate the insulating layer. The annular metal layer is positioned at the interface to prevent plasma from reaching the wiring layer during the dry etching stage, thus eliminating plasma damage while maintaining high aspect ratio through holes.
3Device complexity
If wet etching is used for through hole formation, then the process is simple, but isotropic etching causes void formation and metal material entry
Solution Approach 1:
The annular metal layer serves as a mediator that confines the isotropic etching action of the wet etching solution. It prevents the etching solution from creating lateral voids and entering unintended areas, thus maintaining good through hole geometry control despite using simple isotropic wet etching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents wiring pattern failures and enhances the reliability and compactness of the resonator device by restricting side etching and maintaining high aspect ratio through holes, while using shared materials to reduce manufacturing costs.
Implementation Method 1
penetrating the semiconductor substrate by dry etching
Implementation Method 2
penetrating the insulating layer by wet etching
Data Source
AI summary
A resonator device includes a base and a resonator component disposed on the base. The base includes a semiconductor substrate having a first surface and a second surface that are in a front-to-back relation with each other; an integrated circuit that includes a wiring layer disposed at the second surface side and including a connection pad and includes an insulating layer disposed between the second surface and the wiring layer; a through electrode that penetrates the semiconductor substrate and the insulating layer and is coupled to the connection pad; and an annular metal layer that is disposed so as to penetrate the insulating layer between the second surface and the wiring layer and surrounds the through electrode in a plan view of the semiconductor substrate.