Retention Latch Architecture for Low-Leakage State Preservation
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Solution Overview
Problem
In highly integrated systems like SoCs, powering down circuitry to conserve energy can result in data loss, and incorporating non-volatile memory to preserve data increases costs and power consumption.
Innovation Solution
The implementation of master-slave-retention (MSR) latches that use higher voltage threshold transistors to minimize power consumption while maintaining data integrity by switching to a retention mode, where data is latched and retained using a retention-mode latch with lower leakage currents, and the use of a power mode selector to manage power domains efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If circuitry is powered down to conserve energy, then power consumption is reduced, but data is lost
Solution Approach 1:
The latch is divided into two separate latches: a first latch for active mode operation and a second latch for retention mode. This segmentation allows the system to switch between power-consuming active operation and low-power data retention without data loss, resolving the contradiction between power savings and data preservation.
Solution Approach 2:
Before powering down the circuitry to conserve energy, the data is preliminarily transferred from the first latch to the second latch. This preliminary action ensures data is preserved in the retention-mode latch before the power domain is deactivated, preventing data loss while enabling power savings.
2Loss of information
If non-volatile memory is incorporated to preserve data, then data integrity is maintained, but costs and power consumption increase
Solution Approach 1:
Instead of using expensive non-volatile memory, the patent employs a second latch operating in retention mode with higher voltage threshold transistors. This approach uses simpler, more cost-effective circuitry that consumes minimal power while maintaining data integrity during power-down scenarios.
Solution Approach 2:
The system changes the operating parameters of the second latch by using transistors with higher voltage thresholds and operating in a retention mode rather than active mode. This parameter change enables the latch to maintain data with significantly lower power consumption, avoiding the need for power-intensive non-volatile memory.
3Productivity
If transistor size is reduced to increase functionality, then integration density increases, but leakage currents increase
Solution Approach 1:
The patent applies different transistor characteristics to different parts of the latch circuit. The second latch uses transistors with higher voltage thresholds specifically for retention mode operation, while the first latch uses standard transistors for active mode. This local differentiation allows small transistors to be used throughout while minimizing leakage in the retention path.
Solution Approach 2:
By changing the voltage threshold parameter of transistors in the second latch to higher values, the system reduces leakage currents in the retention-mode circuitry. This parameter change enables the use of smaller transistors for high integration density while maintaining low leakage performance where needed.
Data Source
AI summary
In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.