Retimed Signal Generation Circuit for Low-Jitter Clock Output
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock generation circuits face challenges in reducing jitter due to stationary phase errors caused by offset voltages in phase comparators, leading to variability in clock signal edges and inadequate jitter reduction.
Innovation Solution
A signal generation circuit that includes a phase difference detector, an oscillator with annularly connected delay elements, a low-speed signal generation circuit, and a selection unit to output a low-speed signal in synchronization with an oscillation signal, reducing jitter by integrating phase differences and selecting oscillation signals based on detected phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a DLL with phase comparator and delay elements is used to generate clock signals, then phase difference detection and clock signal generation are achieved, but stationary phase error occurs due to offset voltage causing jitter in the output clock signal
Solution Approach 1:
A retiming circuit is introduced as an intermediary component between the DLL and the output. This retiming circuit uses flip-flops to resynchronize the clock signal edges, effectively removing the stationary phase error caused by offset voltage in the phase comparator while preserving the phase difference detection capability
Solution Approach 2:
The patent implements a feedback mechanism where the output clock signal is fed back to the phase comparator to continuously detect phase differences. This closed-loop feedback system allows real-time correction of phase errors, maintaining both detection precision and signal stability
2Productivity
If retiming is performed using clock signals from DLL with stationary phase error, then clock signal generation is achieved, but jitter is not sufficiently reduced
Solution Approach 1:
The retiming circuit acts as a mediator that separates the clock generation function from the phase error introduction. By placing flip-flops at the output stage, the system maintains high productivity in clock generation while achieving superior jitter reduction quality through edge resynchronization
3Ease of operation
If phase comparator offset voltage is present, then phase difference detection is achieved, but stationary phase error causes variability in clock signal edge intervals
Solution Approach 1:
The retiming flip-flops serve as an intermediary that eliminates the direct impact of offset voltage on edge interval precision. The detection capability is preserved in the phase comparator, while the precision is restored at the output through retiming
Solution Approach 2:
The system performs preliminary phase difference detection and then applies correction through retiming. This two-stage approach allows the phase comparator to operate with offset voltage present while the final output achieves high precision through the preliminary retiming action
Data Source
AI summary
A signal generation circuit includes a phase difference detector configured to detect a phase difference between a certain oscillation signal of a plurality of oscillation signals and a predetermined reference signal; an oscillator to which a plurality of delay elements are connected annularly, the oscillator being configured to generate the plurality of oscillation signals depending on the detected phase difference; a low-speed signal generation circuit configured to generate a low-speed signal having a lower frequency than the oscillation signal; a detection circuit configured to detect a difference between a predetermined reference timing and a timing at which the low-speed signal has changed; a selection unit configured to select the oscillation signal so that the phase difference with respect to the reference signal is close to the detected difference; and an output unit configured to output the generated low-speed signal in synchronization with the selected oscillation signal.