Reverse Embedded GPU Power Structure With TSV Power Delivery
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Solution Overview
Problem
The increasing density of transistors on GPU and SoC chips leads to increased impedance in interconnection lines, which hampers power distribution, heat dissipation, and signal integrity, especially with rising total graphic power requirements.
Innovation Solution
A die structure with through silicon vias (TSVs) and electro-conductive films in the upper space of the chip, providing additional power pathways to transistors, reducing impedance and improving heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of transistors on chip is increased and transistor size is decreased, then the computing power and integration density are improved, but the impedance of interconnection lines increases and power distribution capability deteriorates
Solution Approach 1:
The patent introduces a new vertical dimension for power distribution by embedding power delivery structures within the interconnection layers. Instead of relying solely on traditional planar power rails, the invention uses through-silicon vias (TSVs) and embedded conductive structures that extend vertically through multiple interconnection layers, creating a three-dimensional power distribution network that delivers power directly to transistor regions from above and below the chip substrate.
Solution Approach 2:
The patent embeds power delivery structures within the interconnection layers themselves. Conductive plugs and power vias are nested within the stacked interconnection layer structure, utilizing the vertical space between and within layers. This nesting approach allows power delivery pathways to be integrated within the existing interconnection architecture without requiring separate external power distribution structures.
2Productivity
If the width and thickness of interconnection lines are decreased to accommodate more transistors, then the interconnection density is improved, but the impedance increases and signal integrity deteriorates
Solution Approach 1:
The patent addresses signal integrity by introducing vertical power delivery pathways through TSVs and embedded conductors that reduce the horizontal current flow distance. By delivering power vertically from above and below the chip, the invention reduces the length and impedance of horizontal interconnection lines, thereby improving signal integrity while maintaining high interconnection density.
3Productivity
If more interconnection layers are used to increase the number of interconnections per chip, then the interconnection capacity is improved, but the overall length of interconnection lines increases and power delivery efficiency deteriorates
Solution Approach 1:
The patent reduces power delivery path length by introducing vertical power distribution through TSVs that penetrate through the interconnection layers. Instead of routing power horizontally across multiple layers, the invention delivers power vertically from top and bottom surfaces directly to active regions, significantly reducing the total length of power delivery paths and improving power efficiency despite having multiple interconnection layers.
4Productivity
If transistor density is increased, then the chip performance is improved, but the heat dissipation becomes more difficult
Solution Approach 1:
The patent improves heat dissipation by introducing vertical thermal pathways through the TSV structures and embedded conductors. These vertical structures provide direct thermal conduction paths from hot transistor regions to heat sinks or thermal management structures on the top and bottom surfaces of the chip, enabling more efficient heat removal from high-density transistor regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances power delivery and reduces impedance by up to 50%, improving chip performance and signal integrity while decreasing heat generation.
Implementation Method 1
the power region includes an electro-conductive film on the second body surface and through silicon vias (TSVs) embedded in the power region, wherein for each one of the TSVs, an outer end of the TSV contacts the electro-conductive film and an embedded end of the TSVs contacts one of the power rails of the transistor region
Implementation Method 2
providing additional power pathways independent of conventional interconnection layers, allowing for higher power delivery and reduced impedance
Implementation Method 3
improves heat dissipation by utilizing the upper space of the chip for power pathways
Data Source
AI summary
A die including a die body having a first body surface, a second body surface on an opposite side of the die body as the first body surface, an interconnect region adjacent to the first body surface including interconnect dielectric layers with metal lines and vias, a transistor region above the interconnect region, the metal lines and vias making electrical connections to one or more power rails of the transistor region and electrically connected to transistors of the transistor region, a power region above the transistor region including an electro-conductive film on the second body surface and TSVs in the power region, an outer end of the TSV contacting the film and an embedded end of the TSVs contacting one of the power rails. A method of manufacturing an IC package and computer with the IC package are also disclosed.