Reversed Tone Patterning for Multi-Vt High-K Gate Dielectrics
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Solution Overview
Problem
The formation of integrated circuits with multiple transistors having different threshold voltages is challenging due to difficulties in patterning processes, which can damage high K gate dielectric structures and result in nonfunctioning transistors and poor wafer yields.
Innovation Solution
The use of reversed tone patterning to safely perform dipole drive-in processes that do not significantly damage high K gate dielectric layers, combined with positive tone patterning, allows for the effective formation of multiple threshold voltage regions within integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional patterning processes are used to define different regions for multiple threshold voltages, then transistors with different threshold voltages can be formed, but the high K gate dielectric structures and channel regions are damaged, resulting in nonfunctioning transistors and poor wafer yields
Solution Approach 1:
The patent divides the patterning process into multiple sequential steps: first forming a mandrel pattern, then depositing spacers, selectively removing portions, and repeating the process. This segmentation allows different regions to be defined without exposing the entire wafer to damaging patterning conditions simultaneously, thereby maintaining high K gate dielectric integrity while achieving multiple threshold voltage regions.
Solution Approach 2:
The patent performs preliminary actions by first depositing the high K gate dielectric layer and channel regions before any patterning operations. The mandrel structures are formed preliminarily as sacrificial elements that guide subsequent spacer deposition and pattern transfer, ensuring the sensitive regions are established before exposure to patterning processes.
2Adaptability or versatility
If conventional patterning processes are used to define different regions, then multiple threshold voltage regions can be created, but the threshold voltages of the device regions are not accurate as designed
Solution Approach 1:
The patent applies local quality by using spacer materials with different properties deposited at different locations. The first spacers and second spacers have different compositions or thicknesses, creating locally optimized regions with specific threshold voltages. This local differentiation ensures each region achieves its designed threshold voltage accurately without affecting other regions.
Solution Approach 2:
The patent introduces spacer structures as intermediary elements between the mandrel patterns and the final device regions. These spacers act as mediators that transfer the pattern from mandrels to the active areas while providing precise control over the dimensions and properties of the threshold voltage regions, ensuring manufacturing precision.
3Adaptability or versatility
If dipole drive-in processes are performed to modify threshold voltages, then multiple threshold voltage regions can be formed, but the high K gate dielectric layers are significantly damaged
Solution Approach 1:
The patent converts the potential harm of dipole drive-in processes by using them selectively only in regions where threshold voltage modification is desired, while protecting other regions with mandrel and spacer structures. The process conditions are optimized so that the dipole drive-in modifies threshold voltages accurately without causing significant damage to the high K gate dielectric layers, turning a potentially harmful process into a beneficial tool for creating multiple threshold voltage regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the efficient and accurate formation of multiple threshold voltage regions, leading to properly functioning integrated circuits, higher wafer yields, and improved performance of electronic devices.
Implementation Method 1
performing a first thermal annealing process while the first dipole inducing layer is on the first high-K dielectric layer and on the first hard mask layer over the second channel region
Data Source
AI summary
A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.