Reversible CMOS Fault Detection Without Masked Concurrent Faults
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Solution Overview
Problem
Existing methods for detecting faults in CMOS circuits, such as Dual Modular Redundancy and Triple Modular Redundancy, fail to detect 100% of faults due to the irreversibility of traditional CMOS logic gates, which can mask faults and result in latent faults that do not affect output.
Innovation Solution
The use of reversible and preservative gates to transform logic functions into CMOS circuit equivalents, ensuring that all faults are detectable at the output without masking, through steps like converting irreversible functions to reversible ones and employing ET-MPCMT and Fredkin gates for fault-preserving synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional CMOS logic gates are used for fault detection, then the circuit can operate with standard logic functions, but faults are masked at the output due to irreversibility and don't care conditions, resulting in incomplete fault detection
Solution Approach 1:
The patent changes the fundamental parameter of gate reversibility by replacing traditional irreversible CMOS gates with reversible gates (Fredkin, Toffoli, and their variants). This parameter change eliminates the 'don't care' conditions that cause fault masking in traditional gates, enabling 100% fault detection capability while maintaining CMOS compatibility through the proposed transformation methods
Solution Approach 2:
The patent segments the fault detection problem into two parts: (1) using reversible gates for critical paths where 100% fault detection is required, and (2) using transformation techniques to convert irreversible functions to reversible equivalents. This segmentation allows selective application of complex reversible logic only where necessary, balancing detection completeness with overall circuit complexity
2Reliability
If reversible gates are used to eliminate latent faults, then 100% of switching faults can be detected at the output, but the circuit requires novel gate designs and transformations
Solution Approach 1:
The patent introduces intermediary transformation techniques that bridge traditional irreversible CMOS logic and reversible logic. The transformation methods act as intermediaries, converting standard logic functions into reversible equivalents using Fredkin and Toffoli gates as intermediate building blocks, thereby facilitating easier manufacturing while maintaining 100% fault detection capability
Solution Approach 2:
The patent makes reversible gates universal by demonstrating that both Fredkin and Toffoli gates can implement any logic function and provide 100% fault detection. These universal reversible gates can replace various standard gates (AND, OR, NOT, XOR) through systematic transformation, reducing the need for multiple specialized gate types and simplifying the manufacturing process
Data Source
AI summary
A method of perfect detection of concurrent faults in CMOS circuits, using reversible gates and preservative gates is provided. The concurrent faults occurring in the CMOS circuits are detected without being masked by the method. The method includes the following steps: Carrying out functions using the reversible gates and the preservative gates, transforming the reversible gates and the preservative gates into CMOS circuit equivalents.