RF Power Amplifier Chip Layout to Cut Parasitic Inductance
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Solution Overview
Problem
In semiconductor technologies, parasitic inductance in conductive wire bonding reduces transistor gain, and direct substrate grounding increases chip area and costs due to the need for a back hole design, which can lead to incorrect etching of the source conducting layer and reduced contact with the epitaxial layer.
Innovation Solution
A chip preparation method involving a stacked arrangement of epitaxial and source conducting layers, where the epitaxial layer is formed through front-side lithography to ensure precise contact, reducing the risk of over-etching and allowing for full contact between the epitaxial and source layers, thereby reducing the layout area of the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source is directly grounded through a back hole of the substrate, then parasitic inductance is reduced and transistor performance is improved, but the width of the source metal increases and the chip area increases
Solution Approach 1:
The patent changes the grounding approach from a planar back-hole configuration to a vertical stacked configuration. The epitaxial layer is positioned directly above the source conducting layer, creating a three-dimensional arrangement that reduces the horizontal footprint while maintaining effective grounding connection.
Solution Approach 2:
The patent implements a nested structure where the epitaxial layer is placed within the vertical projection of the source conducting layer. This nesting arrangement allows the grounding function to be achieved within the same horizontal footprint, eliminating the need for additional chip area.
2Manufacturing precision
If front-side lithography is used to form the epitaxial layer, then lithography precision is improved and over-etching is avoided, but the manufacturing process complexity increases
Solution Approach 1:
The patent performs lithography patterning on the front side of the substrate before forming the epitaxial layer. This preliminary action defines the precise pattern that will guide subsequent epitaxial growth, ensuring accurate alignment and preventing over-etching while maintaining process efficiency.
Data Source
AI summary
A method includes: forming, on a substrate (10), an epitaxial layer (11) and a source conducting layer (21), where the epitaxial layer includes a first via, to form a first epitaxial layer (101) of the first transistor and a second epitaxial layer (102) of the second transistor; the source conducting layer includes a first source (211) of the first transistor and a second source (212) of the second transistor; and an edge of the first source (211) is flush with an edge of the first epitaxial layer (101) close to a side of the first via, and an edge of the second source (212) is flush with an edge of the second epitaxial layer (102) close to a side of the first via; forming a first conducting layer (13) in the first via; forming a second via; and forming a second conducting layer (14) in the second via.