RF Transistor Chiplet Bonding With Host-Wafer Bias And Thermal Sensing
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Solution Overview
Problem
There is a need for an electronic assembly that efficiently integrates radio frequency (RF) transistor chiplets with host wafer circuits, allowing for faster manufacturing and lower costs by decoupling the fabrication of chiplet active circuits from passive circuits, while optimizing operating conditions of RF transistors.
Innovation Solution
The integration of RF transistor chiplets into host wafers using lateral bonding material, where chiplets with advanced semiconductor technologies like GaN are combined with CMOS devices on silicon wafers, enabling efficient interconnects and thermal conductivity through metal backfill plugs, and utilizing CMOS transistors for biasing and temperature sensing to optimize RF transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If RF transistor chiplets are integrated into host wafers using lateral bonding, then manufacturing speed and yield are improved, but fabrication process complexity increases
Solution Approach 1:
The system divides the RF circuit fabrication into separate segments: RF transistor chiplets are fabricated independently on separate wafers using specialized processes, while host wafers are fabricated using CMOS processes. This segmentation allows parallel fabrication of different components, improving manufacturing speed and yield while enabling use of different materials and processes for each segment.
Solution Approach 2:
Lateral bonding material serves as an intermediary that connects the RF transistor chiplets to the host wafer circuits. This intermediary enables integration of separately fabricated components, facilitating the heterogeneous integration approach that improves productivity while managing process complexity through standardized bonding interfaces.
2Reliability
If RF transistor chiplets are fabricated separately from host wafers, then fabrication yield is improved, but integration complexity increases
Solution Approach 1:
Separate fabrication of RF transistor chiplets and host wafers allows each to be optimized independently for their specific requirements, improving fabrication yield. The segmentation enables testing and validation of each component separately before integration, reducing the risk of defects in the final assembly.
Solution Approach 2:
The lateral bonding interface provides a universal connection method that can integrate different types of chiplets with different host wafers. This multi-functional bonding approach standardizes the integration process, reducing integration complexity despite the diversity of separately fabricated components.
3Reliability
If heterogeneous materials are used in chiplet integration, then circuit performance is improved, but manufacturing cost increases
Solution Approach 1:
Different materials are used in specific locations where they provide the most benefit: RF transistor chiplets use specialized materials (GaAs, GaN, SiGe) for high-frequency performance, while host wafers use CMOS-compatible materials for cost-effective digital logic. This localized material selection optimizes circuit performance while controlling manufacturing costs by applying expensive materials only where necessary.
Solution Approach 2:
Segmenting the circuit into heterogeneous material regions allows each segment to be fabricated using the most cost-effective process for that specific function. RF analog sections use specialized processes only where needed, while digital sections use standard CMOS processes, reducing overall manufacturing cost while maintaining high performance where required.
4Productivity
If chiplet fabrication is decoupled from host wafer fabrication, then manufacturing scalability is improved, but process coordination difficulty increases
Solution Approach 1:
Decoupling chiplet and host wafer fabrication into separate segments enables independent scaling of each fabrication line. RF transistor chiplets can be produced in high volumes using specialized processes while host wafers are produced using standard CMOS lines, allowing each to be scaled independently based on demand without requiring coordinated production planning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster, cost-effective manufacturing of high-performance RF circuits with improved yield and scalability, optimizing RF transistor performance by decoupling fabrication processes and using CMOS transistors for biasing and temperature monitoring.
Implementation Method 1
enabling efficient interconnects and thermal conductivity through metal backfill plugs
Implementation Method 2
The chiplets may be laterally bonded to the sidewalls of cavities of the wafer, such as using a lateral bonding material
Data Source
AI summary
An electronic assembly heterogeneously integrates radio-frequency (RF) transistor chiplets into a host wafer, and the chiplets have interconnections to host wafer circuits. The assembly has at least one RF transistor chiplet having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT). The host wafer has at least one host wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT. The host wafer circuit includes first circuitry to provide a DC bias of the HEMT or HBT; or second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT. The electrical interconnects are between the chiplet and the wafer, and electrically connect the host wafer circuit to the chiplet circuit.