RF Receiver Clock Retiming for Digital Interference Mitigation
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Solution Overview
Problem
Integrated circuits with both digital and RF components face interference issues when operating concurrently, leading to degradation in RF performance, which is mitigated by preventing RF component operation, limiting flexibility and speed.
Innovation Solution
An interference mitigation circuit that dynamically adjusts clock signals by phase delaying or retiming them when the RF receiver is active, using a latch and flop to synchronize data with the source clock, and a clock generation circuit that switches between source and phase-delayed clock signals to minimize interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If RF components operate concurrently with digital modules, then system flexibility and operation speed are improved, but RF performance degrades due to interference
Solution Approach 1:
The patent applies dynamics by making the clock signal phase adjustable based on RF receiver activity. The phase of the clock signal dynamically changes between a first phase when the RF receiver is inactive and a second phase when it is active, allowing the system to adapt its timing characteristics to minimize interference while maintaining concurrent operation capability.
Solution Approach 2:
The patent changes the phase parameter of the clock signal depending on RF receiver state. By modifying the phase characteristic of the clock signal used by digital modules, the system optimizes timing to reduce interference with RF operations while maintaining data transmission functionality.
2Speed
If RF components operate concurrently with digital modules, then operation speed is improved, but interference increases
Solution Approach 1:
The system dynamically adjusts clock signal phase based on RF receiver activity state, enabling concurrent operation at full speed while minimizing interference through adaptive timing adjustments.
Solution Approach 2:
The clock signal operates with different phase characteristics during different operational periods - using a first phase during RF inactive periods and a second phase during RF active periods, creating a periodic adaptation pattern that reduces interference while maintaining continuous operation.
3Reliability
If clock signal phase is adjusted to reduce interference, then RF performance is improved, but data synchronization complexity increases
Solution Approach 1:
The latch circuit dynamically adjusts its timing characteristic based on RF receiver activity, using a first timing characteristic when RF is inactive and a second timing characteristic when RF is active. This dynamic adaptation simplifies synchronization by automatically adjusting to the appropriate timing mode rather than requiring complex continuous adjustment mechanisms.
Solution Approach 2:
The patent segments the operation into distinct modes - a first mode for RF inactive periods and a second mode for RF active periods. Each mode uses a simplified, fixed timing characteristic, avoiding the need for complex continuous synchronization algorithms while maintaining overall system reliability.
Data Source
AI summary
In one example, an apparatus includes: a radio frequency (RF) receiver to receive an RF signal; a media access control (MAC) circuit to receive data and output MAC-processed data according to a clock signal that is phase delayed with respect to a source clock signal when the RF receiver is active; and an interference mitigation circuit to receive the MAC-processed data and provide the MAC-processed data to a physical circuit resynchronized to the source clock signal.