RF Switch FET Stack Bias Network for Leakage and Q Tradeoffs
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Solution Overview
Problem
RF switch circuits using FETs face issues with high leakage current due to accumulated charge in SOI FETs, which degrades breakdown voltage and harmonic performance, necessitating an improved switch stack design.
Innovation Solution
The implementation of mixed-style gate resistor bias networks in switch stacks comprising ACS FETs, combining rung and rail configurations to mitigate leakage current effects, and the use of novel mixed-style body resistor bias networks in non-ACS FET stacks, allowing for a tradeoff between adverse Vg offset and Q factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FETs are used in RF switch circuits, then switching functionality is achieved, but leakage current increases due to accumulated charge in SOI FETs
Solution Approach 1:
The patent divides the FET stack into multiple segments with separate bias networks. Each FET or group of FETs has its own gate resistor configuration (rung or rail), allowing independent control and mitigation of leakage current effects in different portions of the stack.
Solution Approach 2:
The patent applies different bias network configurations (rung vs rail) to different portions of the FET stack based on local requirements. ACS FETs with high leakage current are paired with specific resistor configurations optimized for their location and characteristics, rather than using a uniform approach.
2Manufacturing precision
If ACS FETs are used to improve linearity, then accumulated charge is reduced, but leakage current increases degrading breakdown voltage
Solution Approach 1:
The patent introduces carefully selected resistor elements as intermediary components between the ACS FETs and the bias voltage sources. These resistors act as mediators that control the flow of leakage current while maintaining the linearity benefits of ACS FETs, preventing direct degradation of breakdown voltage.
Solution Approach 2:
The patent optimizes the resistance values and configurations (rung vs rail) to change the electrical parameters of the bias network. By adjusting resistor values and topology, the system maintains ACS FET linearity while controlling leakage current effects on breakdown voltage through parameter optimization.
3Reliability
If gate resistor values are reduced to mitigate leakage current effects, then Vg offset is reduced, but Q factor decreases
Solution Approach 1:
The patent creates a dynamic bias network where the effective gate resistance is adjusted based on the specific FET characteristics and position in the stack. ACS FETs with high leakage are paired with lower resistance configurations, while other FETs use higher resistance to maintain Q factor, creating an optimized dynamic balance rather than a static uniform resistance value.
Data Source
AI summary
Embodiments include a switch stack comprising ACS FETs and mixed-style gate resistor bias networks that mitigate the effects of high leakage current. By carefully selecting the number of ACS FETs in a sub-stack that uses a rung gate resistor bias network versus a sub-stack that uses a rail gate resistor bias network, as well as by selecting particularly useful values for the gate resistors in each bias network, a tradeoff can be achieved between adverse Vg offset and Q factor. The switch stack may be configured with rung-rail gate resistor bias networks, or with rung-rail-rung gate resistor bias networks. Other embodiments include mixed-style body resistor bias networks in switch stacks comprising non-ACS FETs. Some embodiments include one or more positive-logic FETs M1-Mn, series-coupled on at least one end to an “end-cap” FET M0 of a type that turns OFF when the applied VGS is essentially zero volts.