RF Switch FET Stack Layout for Higher Voltage With Lower Ron

The patent applies local quality by implementing a non-uniform distribution of gate lengths among FETs in the stack, where FETs experiencing higher voltage stress have longer gate lengths for enhanced breakdown voltage, while FETs with lower voltage stress have shorter gate lengths to minimize ON-resistance. This localized optimization resolves the contradiction by matching each FET's physical parameters to its specific electrical stress conditions within the stack.

The patent implements local quality by varying gate lengths of individual FETs based on their position and voltage stress in the stack. FETs subjected to higher voltage stress are assigned longer gate lengths to maintain breakdown voltage margins and prevent avalanche breakdown, which would cause non-linear distortion. This localized parameter optimization ensures each FET operates within its linear region under its specific stress conditions, thereby maintaining overall linearity performance while achieving high voltage handling capacity.

The patent applies parameter changes by modifying the gate length parameter of FETs in the stack according to a non-uniform distribution pattern. Instead of using identical FETs throughout the stack, the gate length is varied systematically based on voltage stress considerations. This parameter variation allows the use of standard FET fabrication processes while achieving optimized performance, thereby limiting the increase in device complexity to merely an additional design parameter rather than fundamental structural complexity.