RF Switch Gate Timing for Fast Switching and Isolation
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Solution Overview
Problem
Conventional RF switching devices face a trade-off between switching time and isolation properties, where improving switching time often degrades isolation, and maintaining isolation increases switching time, especially in power amplifiers using time division duplex methods.
Innovation Solution
The RF switching device incorporates a delay circuit that generates gate signals with different switching times for individual transistors, using a combination of inverters and variable capacitors to adjust delay times, allowing for independent control of switching times and reducing clock feed-through impacts without degrading isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate resistor value is reduced to improve switching time, then switching speed increases, but isolation properties degrade
Solution Approach 1:
The gate resistor is divided into multiple segments (first gate resistor and second gate resistor) connected in series between the gate buffer and the transistor gate. This segmentation allows independent optimization of each resistor's function: the first resistor controls switching speed while the second resistor maintains isolation properties, resolving the contradiction between fast switching and good isolation.
Solution Approach 2:
Different portions of the gate resistor circuit are assigned different resistance values to perform different functions. The first gate resistor has a lower resistance value optimized for fast switching, while the second gate resistor has a higher resistance value optimized for isolation, allowing each component to excel at its specific function rather than compromising overall performance.
2Reliability
If the gate resistor value is increased to maintain isolation properties, then isolation improves, but switching time increases
Solution Approach 1:
The gate resistor is divided into multiple segments (first gate resistor and second gate resistor) connected in series between the gate buffer and the transistor gate. This segmentation allows independent optimization of each resistor's function: the first resistor controls switching speed while the second resistor maintains isolation properties, resolving the contradiction between fast switching and good isolation.
Solution Approach 2:
Different portions of the gate resistor circuit are assigned different resistance values to perform different functions. The first gate resistor has a lower resistance value optimized for fast switching, while the second gate resistor has a higher resistance value optimized for isolation, allowing each component to excel at its specific function rather than compromising overall performance.
3Area of stationary object
If the device size is reduced to improve integration, then area decreases, but switching performance may be compromised
Solution Approach 1:
The delay circuit is integrated within the existing RF switching device structure, combining multiple functions (signal delay, gate signal generation, and switching control) into a single compact unit. This merging approach achieves fast switching performance without proportionally increasing the device area, as the delay circuit shares physical space and resources with other device components.
Data Source
AI summary
A radio frequency switching device includes a switching circuit including first and second transistors; a gate resistor circuit including a first gate resistor and a second gate resistor, the first gate resistor connected to a gate of the first transistor and the second gate resistor connected to a gate of the second transistor; a gate buffer circuit including a first gate buffer and a second gate buffer, the first gate buffer being connected to the first gate resistor to provide a first gate signal to the first transistor through the first gate resistor, the second gate buffer being connected to the second gate resistor to provide a second gate signal to the second transistor through the second gate resistor; and a delay circuit to generate the first gate signal having a first switching time and the second gate signal having a second switching time different than the first switching time.


