RF Field-Effect Transistor Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing radio-frequency switches face challenges in reducing parasitic capacitance between the gate electrode and wiring lines, contact plugs, and other components, which affects the off-capacitance and overall loss in radio-frequency devices.
Innovation Solution
Incorporating a low-dielectric constant region between the first metals along the in-plane direction of the semiconductor layer, specifically below the bottom surfaces of the metals, to reduce parasitic capacitance and extrinsic off-capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional gate electrode structure is used, then the device structure is simple, but the parasitic capacitance between the gate electrode and contact plug cannot be sufficiently reduced
Solution Approach 1:
A low-dielectric constant region is introduced as an intermediary between the gate electrode and the contact plug. This intermediate layer with reduced dielectric constant (lower than surrounding regions) acts as a mediator to decrease the electric field coupling and thus reduce the parasitic capacitance between the gate electrode and contact plug, without requiring complex structural modifications
Solution Approach 2:
The dielectric constant parameter of the region between the gate electrode and contact plug is changed by introducing a low-dielectric constant material or structure. By reducing the dielectric constant in this specific region compared to conventional structures, the parasitic capacitance is reduced while maintaining the overall device structure simplicity
2Area of stationary object
If wiring lines are placed close to contact plugs, then the device area is reduced, but the inter-wiring capacitance and parasitic capacitance increase
Solution Approach 1:
The dielectric constant is made non-uniform by introducing a low-dielectric constant region specifically in the area between the gate electrode and contact plug. This local modification of dielectric quality allows wiring lines to be placed closer to contact plugs without significantly increasing parasitic capacitance, as the low-dielectric constant region is localized to the critical area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively minimizes the extrinsic component of off-capacitance, leading to reduced loss in radio-frequency switches by decreasing the product of on-resistance and off-capacitance, thereby enhancing the performance of radio-frequency devices.
Implementation Method 1
a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction
Data Source
AI summary
There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.