RFIC CDM Protection via De-Q and Cascode Circuitry
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Radio frequency integrated circuits (RFICs) in wireless devices are vulnerable to electrostatic discharge (ESD), which can cause damage due to the susceptibility of transistors fabricated with sub-micron CMOS processes, and existing ESD protection circuits may compromise performance during charged-device model (CDM) testing.
Innovation Solution
The implementation of a charged-device model protection circuitry that includes de-Q circuitry and a cascode device, which limits current through parasitic paths and directs ESD through diodes, maintaining gate-to-source voltage below failure points, and a cascode device that turns on during negative ESD events to increase source potential and protect the input device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sub-micron CMOS fabrication processes are used for RF circuits, then cost is reduced and integration is improved, but transistors become more susceptible to electrostatic discharge (ESD) damage
Solution Approach 1:
The patent introduces diodes as intermediary protection elements connected to the gate terminal. These diodes act as mediators that capture and divert ESD energy away from the vulnerable sub-micron transistor, allowing the use of cost-effective sub-micron CMOS processes while maintaining reliability against ESD damage.
2Reliability
If ESD protection circuits are added to protect RFICs, then reliability against ESD is improved, but performance during charged-device model (CDM) testing deteriorates
Solution Approach 1:
The patent applies ESD protection selectively at the gate terminal where it is most needed, rather than throughout the entire circuit. The diodes are specifically positioned to protect the gate-to-source voltage, providing localized protection that maintains overall circuit performance during CDM testing while still offering reliable ESD protection.
3Reliability
If existing ESD protection circuits are used, then some protection is provided, but gate-to-source voltage exceeds failure points during ESD events
Solution Approach 1:
The patent converts the harmful ESD energy into a beneficial protective mechanism. The diodes are designed to become conductive during ESD events, intentionally creating a controlled discharge path that converts the harmful voltage buildup into a safe, controlled current flow that protects the transistor from damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively protects RFICs from ESD without degrading input match, noise figure, or linearity, allowing them to pass CDM testing and reducing the risk of failure during both positive and negative ESD events.
Implementation Method 1
The de-Q circuitry may limit current through a parasitic path of the n-channel transistor, reducing voltage buildup between the gate of the n-channel transistor and the source of the n-channel transistor
Implementation Method 2
The de-Q circuitry may direct electrostatic discharge through a +ve diode coupled between the ground pad and the input signal pad
Implementation Method 3
The cascode device may turn on the input device during -ve electrostatic discharge. Turning on the input device may increase a source potential of the input device, protecting the gate-to-source of the input device
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An apparatus is described. The apparatus includes an input device. The apparatus also includes a positive supply voltage pad. The apparatus further includes an input signal pad. The apparatus also includes a ground pad. The apparatus further includes charged-device model protection circuitry that protects the input device from electrostatic discharge. The charged-device model protection circuitry includes at least one of de-Q circuitry and a cascode device.