Rhombus Fin Semiconductor Gate Control
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Solution Overview
Problem
The short channel effect and limited carrier mobility in semiconductor devices due to rectangular silicon fins and weak gate control capability, which hinder the reduction of device size and performance.
Innovation Solution
The use of rhombus-like fins with a quantum well layer made of SiGe alloy and a gate stack structure comprising high-K and metal materials, along with raised source and drain regions, to enhance gate control and carrier limitation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If rectangular silicon fins are used with conformal gate control, then the manufacturing process is simple, but the gate control capability is weak and short channel effect cannot be suppressed
Solution Approach 1:
The patent applies asymmetry by changing the fin cross-section from rectangular to trapezoidal shape. The trapezoidal fin has a wider top width than bottom width, creating an asymmetric geometry that improves gate control capability over the channel region while maintaining manufacturing feasibility through controlled epitaxial growth and etching processes.
Solution Approach 2:
The patent introduces local quality by adding a quantum well layer specifically at the interface between the fin and gate stack structure. This localized modification with SiGe alloy creates enhanced carrier confinement and control in the critical gate-fin interface region without altering the entire fin structure, thereby improving gate control capability where it is most needed.
2Productivity
If device size is reduced to improve integration density, then more devices can be packed, but short channel effect occurs due to reduced channel length
Solution Approach 1:
The asymmetric trapezoidal fin geometry extends the effective gate control region along the channel length. The wider top portion provides better gate overlap and control over the channel, allowing effective suppression of short channel effect even when the overall device dimensions are reduced for higher integration density.
Solution Approach 2:
The quantum well layer is strategically positioned at the gate-fin interface to provide localized carrier confinement. This local enhancement of control mechanism compensates for the reduced channel length in scaled devices, maintaining effective gate control and suppressing short channel effects despite smaller device dimensions.
3Ease of manufacture
If conventional rectangular fins are used, then the etching process is straightforward, but the surface area to volume ratio is small limiting gate control
Solution Approach 1:
The trapezoidal fin geometry increases the surface area exposed to the gate stack structure compared to rectangular fins of the same volume. The slanted sides and wider top create additional gate-fin interface area, improving the surface area to volume ratio and enhancing gate control capability while maintaining etching process feasibility through anisotropic etching methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the short channel effect and improves carrier mobility, thereby enhancing the overall performance and drive capability of the semiconductor device.
Implementation Method 1
a quantum well as well as the method for manufacturing the same... a quantum well layer is disposed between the fins and the gate stack structure... the quantum well layer comprises a SiGe alloy
Implementation Method 2
fins on a substrate, which extend along a first direction and which have rhombus-like cross-sections... the width at the middle of the fin having a rhombus-like cross-section is greater than the width at the bottom thereof
Data Source
AI summary
The present invention discloses a method for manufacturing a semiconductor device, which comprises: forming a plurality of fins on a substrate, which extend along a first direction and have rhombus-like cross-sections; forming a gate stack structure on each fin, which traverses the plurality of fins and extends along a second direction; wherein a portion in each fin that is under the gate stack structure forms a channel region of the device, and portions in each fin that are at both sides of the gate stack structure along the first direction form source and drain regions. The semiconductor device and its manufacturing method according to the present invention use rhombus-like fins to improve the gate control capability to effectively suppress the short channel effect, moreover, an epitaxial quantum well is used therein to better limit the carriers, thus improving the device drive capability.