Ribbon CFET Metal Gate Layout for Multi-Threshold Integration
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Solution Overview
Problem
The integration of complementary field-effect transistors (CFETs) in logic devices and memory devices faces challenges in balancing performance requirements with power constraints, particularly in applications involving accelerators like Tile Matrix Multiply (TMUL) units and Vision Processing Units (VPU), where existing transistor architectures struggle to optimize threshold voltage for efficient power management.
Innovation Solution
The implementation of a CFET structure with integrated multiple threshold voltages (Vt) using volumeless nD and pD for Vt separation, allowing independent control of threshold voltages through different combinations of NMOS and PMOS dipole doses, enabling a balanced performance and power consumption across various applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single threshold voltage is used in CFETs, then the device structure is simple, but performance and power consumption cannot be optimized for different applications
Solution Approach 1:
The CFET device is segmented into multiple independent threshold voltage regions by introducing dipole layers at specific interfaces. Each dipole layer creates a distinct threshold voltage level, allowing the device to be divided into regions with different electrical characteristics while maintaining a unified physical structure.
Solution Approach 2:
Different dipole layer configurations are applied to different regions of the CFET device to create local variations in threshold voltage. The first dipole layer at the first interface and the second dipole layer at the second interface provide locally optimized threshold voltages tailored to specific functional requirements within the device.
2Productivity
If multiple threshold voltages are integrated into CFETs, then performance and power consumption are optimized, but the manufacturing process becomes more complex
Solution Approach 1:
The dipole layers are incorporated into the CFET structure during the initial fabrication process, before the device is fully assembled and tested. This preliminary integration of threshold voltage control mechanisms allows for optimized performance to be built-in from the start, avoiding the need for complex post-fabrication adjustments or multiple device types.
3Loss of energy
If higher threshold voltage is used, then power consumption is reduced, but device speed decreases
Solution Approach 1:
The device enables dynamic selection of threshold voltage levels by allowing different regions to operate at different threshold voltages simultaneously. This dynamic capability permits the device to switch between power-efficient and speed-optimized modes depending on the operational requirements of different circuit segments.
Data Source
AI summary
A stacked complementary field-effect device (CFET) device includes a bottom contact region and a top contact region. A plurality of stacked CFET devices is between the bottom contact region and the top contact region. Respective ones of the plurality of stacked CFET devices comprise a first transistor layer of a first type over the bottom contact region, and a second transistor layer of a second type over the first transistor layer. The first transistor layer comprises a first plurality of channels surrounded by a first metal gate stack, and the second transistor layer comprises a second plurality of channels surrounded by a second metal gate stack, wherein the respective ones of the plurality of stacked CFET devices include different combinations of N dipole doses and a P dipole dose in both the first metal gate stack and the second metal gate stack.