Ring Oscillator Frequency Divider With Non-Overlapping MOSFET Stages
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Solution Overview
Problem
Conventional ring oscillator frequency dividers face limitations due to significant parasitic capacitance, power consumption, and minimum operating frequency issues caused by the size disparity between PMOS and NMOS FETs, as well as simultaneous turning on of PMOS and NMOS FETs, which affects their performance and efficiency.
Innovation Solution
A ring oscillator frequency divider design that enables each cascaded inverter stage to be turned on substantially one at a time, using a control circuit to generate independent control voltages for NMOS FETs, reducing the need for larger PMOS FETs and minimizing simultaneous FET activation, thereby reducing parasitic capacitance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If PMOS and NMOS FETs are simultaneously turned on in conventional ring oscillator frequency dividers, then the circuit operation is simplified, but parasitic capacitance and power consumption increase significantly
Solution Approach 1:
The patent segments the FET activation process by introducing separate control circuits for PMOS and NMOS FETs. Each FET type is controlled independently through dedicated control signals (CP for PMOS, CN for NMOS), preventing simultaneous turning on and reducing parasitic capacitance effects while maintaining circuit functionality.
Solution Approach 2:
The patent implements periodic non-overlapping control signals that activate PMOS and NMOS FETs in alternating phases. The control circuit generates periodic pulses that ensure one FET type is active while the other is off, creating a sequential operation pattern that reduces power consumption and parasitic effects.
2Stability of the object's composition
If PMOS FETs are made larger to compensate for size disparity with NMOS FETs, then circuit balance is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies different control strategies to PMOS and NMOS FETs based on their inherent characteristics. By providing localized control circuits that generate appropriate control signals for each FET type, the patent optimizes their individual performance without requiring uniform sizing, thereby maintaining circuit balance while minimizing parasitic capacitance.
Solution Approach 2:
The patent changes the control parameters (timing, duration, and amplitude of control signals) for PMOS and NMOS FETs to compensate for size disparities. Through parameter optimization rather than physical size matching, the patent achieves circuit balance while keeping FET sizes small to reduce parasitic capacitance.
3Adaptability or versatility
If minimum operating frequency is reduced for better low-frequency performance, then frequency range is expanded, but circuit reliability deteriorates
Solution Approach 1:
The patent incorporates feedback mechanisms in the control circuits that monitor the operating state of the ring oscillator and adjust control signal parameters accordingly. This feedback ensures stable operation across a wide frequency range while maintaining circuit reliability by preventing unstable states at low frequencies.
Solution Approach 2:
The patent implements dynamic control where the control circuit adjusts its operation based on the desired output frequency. For low-frequency operation, the control circuit extends the activation periods of FETs, while for high-frequency operation, it shortens them, thereby adapting the circuit behavior to maintain reliability across the entire frequency range.
Data Source
AI summary
Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the input clock, enables each of a ring of N cascaded inverter stages substantially one at a time in response to the input clock; and outputs a second clock from an output of one of the ring of N cascaded inverter stages. In one aspect, each stage includes a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET). In another, each stage includes two PMOS FETs and an NMOS FET.