Ring Gate Transistor for Flash Memory Edge Fringing Field Reduction
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Solution Overview
Problem
Charge trapping flash memories face reliability issues due to shallow trench isolation (STI) edge fringing field effects, which cause abnormal subthreshold current, affect program/erase speed, and lead to device variation, especially as these memories are scaled down.
Innovation Solution
A memory cell structure with a ring-shaped gate or gates surrounding a terminal, implemented on a planar substrate without trench isolation, providing a semiconductor body with a channel region and a control gate that surrounds the terminal, enhancing data retention and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If shallow trench isolation (STI) is used in near planar or FinFET structures, then device fabrication is enabled, but edge fringing field effects occur causing abnormal subthreshold current and degraded reliability
Solution Approach 1:
The patent removes the STI structure entirely from the memory cell design, extracting the harmful edge fringing field effect source. Instead of using STI for isolation, the invention employs a ring gate structure that achieves both device fabrication capability and eliminates the reliability-degrading fringing fields at the STI edges
Solution Approach 2:
The patent inverts the conventional approach by placing the gate structure in a ring configuration surrounding the channel, rather than using traditional planar or FinFET geometries with STI. This inversion of the gate architecture fundamentally changes the electric field distribution, eliminating the harmful fringing effects while maintaining fabrication feasibility
2Quantity of substance
If memory cells are scaled down to increase density, then storage capacity increases, but STI edge fringing field effects worsen causing larger device variation and degraded ISPP slope
Solution Approach 1:
The patent transitions from two-dimensional planar or FinFET structures to a three-dimensional ring gate configuration. This dimensional change allows the gate to surround the channel completely, providing uniform control and eliminating the edge fringing field effects that cause device variation, while enabling continued scaling for increased density
3Quantity of substance
If conventional planar or FinFET structures are used, then high density memory arrays can be formed, but data retention characteristics are degraded due to fringing field effects
Solution Approach 1:
The ring gate structure nests the channel region within the gate structure, creating a configuration where the gate completely surrounds the channel. This nested arrangement provides uniform electric field control and eliminates the external STI fringing fields that degrade data retention, while maintaining high density through efficient space utilization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed memory cell structure improves data retention and reliability by reducing edge fringing field effects, leading to more consistent program/erase operations and increased density in memory arrays, thus enhancing the overall performance of charge trapping flash memories.
Implementation Method 1
A voltage applied to the control gate can change the current through the channel region, as required by operations to write, read and erase a ring gate memory cell
Implementation Method 2
Memory material is disposed over the channel region, and can include a dielectric charge storage structure
Data Source
AI summary
A memory device includes a semiconductor body having a first conductivity type, a first terminal in the semiconductor body having a second conductivity type, a channel region having the first conductivity type surrounding the first terminal, and a second terminal having the second conductivity type surrounding the channel region. A connector is in contact with the first terminal, and can be connected to a bit line in an overlying patterned conductor layer. Memory material is disposed over the channel region, and can include a dielectric charge storage structure. A control gate surrounds the first terminal and is disposed over the memory material. A conductive line surrounds the control gate and is in contact with the second terminal. The control gate and the conductive line can be ring shaped.